AN 744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices

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ID 683785
Date 5/13/2016
Public
Document Table of Contents
Document Table of Contents x
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices x
1.1. Block Diagrams 1.2. Design Components 1.3. Design Parameters 1.4. Hardware and Software Requirements 1.5. Using the Reference Design 1.6. Upgrading the Components 1.7. Testbench 1.8. Interface Signals 1.9. Configuration Registers 1.10. Document Revision History
1.7. Testbench x
1.7.1. Testbench Files 1.7.2. Simulating the Testbench 1.7.3. Test Case: Design With the IEEE 1588v2 Feature 1.7.4. Test Case: Design Without the IEEE 1588v2 Feature
1.8. Interface Signals x
1.8.1. Packet Classifier Interface Signals 1.8.2. ToD Interface Signals
1.9. Configuration Registers x
1.9.1. ToD Registers 1.9.2. Packet Generator Registers 1.9.3. Traffic Monitor Registers
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices

1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices

The Altera® scalable Triple-Speed Ethernet reference designs demonstrate the functionalities of the Altera Triple-Speed Ethernet MegaCore® in Arria 10 devices. The reference designs offer the following features:

  • Multi-channel Triple-speed Ethernet MAC IP operating at 10/100/1000 Mbps.
  • Scability, up to 10 Ethernet channels.
  • Implementation of the IEEE 1588v2 feature in one of the designs.
  • Packet monitoring on the TX and RX datapaths.
  • Reporting of the MAC TX and RX statistics counters.
  • Testing of various types of Ethernet packet transfer.

Section Content
Block Diagrams
Design Components
Design Parameters
Hardware and Software Requirements
Using the Reference Design
Upgrading the Components
Testbench
Interface Signals
Configuration Registers
Document Revision History

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