AN 744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices

ID 683785
Date 5/13/2016
Public

1.7.4. Test Case: Design Without the IEEE 1588v2 Feature

The simulation performs the following steps.

  1. Starts up the design with an operating speed of 1 Gbps.
  2. Configures the MAC, PHY speed, and FIFO buffer for the channels.
  3. Waits until the design asserts the channel_ready signal for each channel.
  4. Sends the following packets:
    • Basic data frame, 64 bytes.
    • VLAN multicast data frame, 1000 bytes.
    • Basic data frame, 800 bytes.
    • SVLAN broadcast data frame, 80 bytes.
    • VLAN unicast data frame, 500 bytes.
    • SVLAN data frame, 1500 bytes.
  5. Repeats steps 2 to 4 for operating speeds 100 Mbps and 10 Mbps.

When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully.

Figure 6. Simulation Results

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