1.1. Block Diagrams
The following diagrams show the components of the reference designs, and their clocking and reset schemes.
- Master reset—resets all channels when the active-low signal, master_reset_n, is asserted. Altera recommends that you trigger the master reset upon power-up, when the FPGA is successfully configured.
- Channel reset—resets channel n when the active low signal, channel_reset_n[n], is asserted.
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