AN 744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices

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ID 683785
Date 5/13/2016
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Document Table of Contents
Document Table of Contents x
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices x
1.1. Block Diagrams 1.2. Design Components 1.3. Design Parameters 1.4. Hardware and Software Requirements 1.5. Using the Reference Design 1.6. Upgrading the Components 1.7. Testbench 1.8. Interface Signals 1.9. Configuration Registers 1.10. Document Revision History
1.7. Testbench x
1.7.1. Testbench Files 1.7.2. Simulating the Testbench 1.7.3. Test Case: Design With the IEEE 1588v2 Feature 1.7.4. Test Case: Design Without the IEEE 1588v2 Feature
1.8. Interface Signals x
1.8.1. Packet Classifier Interface Signals 1.8.2. ToD Interface Signals
1.9. Configuration Registers x
1.9.1. ToD Registers 1.9.2. Packet Generator Registers 1.9.3. Traffic Monitor Registers
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices

1.1. Block Diagrams

The following diagrams show the components of the reference designs, and their clocking and reset schemes.

Figure 1. Block Diagram of the Reference Design Without the IEEE 1588v2 Feature
Figure 2. Block Diagram of the Reference Design With the IEEE 1588v2 Feature
The designs consist of two asynchronous reset domains:
  • Master reset—resets all channels when the active-low signal, master_reset_n, is asserted. Altera recommends that you trigger the master reset upon power-up, when the FPGA is successfully configured.
  • Channel reset—resets channel n when the active low signal, channel_reset_n[n], is asserted.
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