AN 744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices

ID 683785
Date 5/13/2016
Public

1.1. Block Diagrams

The following diagrams show the components of the reference designs, and their clocking and reset schemes.

Figure 1. Block Diagram of the Reference Design Without the IEEE 1588v2 Feature
Figure 2. Block Diagram of the Reference Design With the IEEE 1588v2 Feature
The designs consist of two asynchronous reset domains:
  • Master reset—resets all channels when the active-low signal, master_reset_n, is asserted. Altera recommends that you trigger the master reset upon power-up, when the FPGA is successfully configured.
  • Channel reset—resets channel n when the active low signal, channel_reset_n[n], is asserted.

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