AN 744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices

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ID 683785
Date 5/13/2016
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Document Table of Contents
Document Table of Contents x
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices x
1.1. Block Diagrams 1.2. Design Components 1.3. Design Parameters 1.4. Hardware and Software Requirements 1.5. Using the Reference Design 1.6. Upgrading the Components 1.7. Testbench 1.8. Interface Signals 1.9. Configuration Registers 1.10. Document Revision History
1.7. Testbench x
1.7.1. Testbench Files 1.7.2. Simulating the Testbench 1.7.3. Test Case: Design With the IEEE 1588v2 Feature 1.7.4. Test Case: Design Without the IEEE 1588v2 Feature
1.8. Interface Signals x
1.8.1. Packet Classifier Interface Signals 1.8.2. ToD Interface Signals
1.9. Configuration Registers x
1.9.1. ToD Registers 1.9.2. Packet Generator Registers 1.9.3. Traffic Monitor Registers
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices

1.9.1. ToD Registers

The Master and Slave ToDs are present in the design with the IEEE 1588v2 feature.

Table 9.  ToD Register Map
Byte Offset Name Description Access Reset Value
0x00 SecondsH
  • Bits [15:0]: The upper 16 bits of the second field.
  • Bits [31:16]: Reserved.
 RW 0xffffffff
0x04 SecondsL The lower 32 bits of the second field. RW 0x0
0x08 NanoSec The nanosecond field. RW 0x0
0x10 Period
  • Bits [15:0]: The time-of-day in fractional nanosecond.
  • Bits [19:16]: The time-of-day in nanosecond.
  • Bits [31:20]: Reserved
 RW 0x0
0x14 AdjustPeriod The offset adjustment period.
  • Bits [15:0]: The period in fractional nanosecond.
  • Bits [19:16]: The period in nanosecond.
  • Bits [31:20]: Reserved
 RW 0x0
0x18 AdjustCount
  • Bits [19:0]: The number of adjusted period in clock cycles.
  • Bits [31:20]: Reserved
 RW 0x0
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