AN 744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices

ID 683785
Date 5/13/2016
Public

1.8. Interface Signals

Table 5.  Top-level Design Signals
Signal Direction Width Description
ref_clk In 1 125-MHz reference clock for the design.
mm_clk In 1 50-MHz clock for Avalon-MM interface.
channel_reset_n[] In NUM_CHANNELS An asynchronous and active-low reset signal that resets individual Ethernet channels. This signal does not reset the components shared by all channels, such as the master TOD, master PPS, reconfig bundle, and fPLLs.
master_reset_n In 1 An asynchronous and active-low reset signal that resets the entire design.
led_link_n Out NUM_CHANNELS When asserted, this active-low signal indicates a successful link synchronization.
rx_serial_data In NUM_CHANNELS RX serial data.
tx_serial_data Out NUM_CHANNELS TX serial data.
sfpa_mod1_scl Bidir 1 Serial clock line of the I2C interface.
sfpa_mod2_sda Bidir 1 Serial data line of the I2C interface.
sfp_txdisable Out 1 Deasserted to enable the transmitter optical output.
xfp_txdisable Out 1 Deasserted to enable the transmitter optical output.

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