AN 744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices

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ID 683785
Date 5/13/2016
Public
Document Table of Contents
Document Table of Contents
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices
1.1. Block Diagrams 1.2. Design Components 1.3. Design Parameters 1.4. Hardware and Software Requirements 1.5. Using the Reference Design 1.6. Upgrading the Components 1.7. Testbench 1.8. Interface Signals 1.9. Configuration Registers 1.10. Document Revision History
1.7. Testbench
1.7.1. Testbench Files 1.7.2. Simulating the Testbench 1.7.3. Test Case: Design With the IEEE 1588v2 Feature 1.7.4. Test Case: Design Without the IEEE 1588v2 Feature
1.8. Interface Signals
1.8.1. Packet Classifier Interface Signals 1.8.2. ToD Interface Signals
1.9. Configuration Registers
1.9.1. ToD Registers 1.9.2. Packet Generator Registers 1.9.3. Traffic Monitor Registers
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices

1.9.3. Traffic Monitor Registers

Table 11.  Traffic Monitor Register Map
Byte Offset Name Description Access Reset Value
0x00 RXPKTCNT_EXPT The number of packets that the traffic monitor expects to receive. RW 0xffffffff
0x04 RXPKTCNT_GOOD The number of good packets received by the traffic monitor. RO 0x0
0x08 RXPKTCNT_BAD The number of packets received with CRC error. RO 0x0
0x0C RXBYTECNT_LO32 The lower 32 bits of the counter that keeps track of the total number of bytes the traffic monitor received. RO 0x0
0x10 RXBYTECNT_HI32 The upper 32 bits of the counter that keeps track of the total number of bytes the traffic monitor received. RO 0x0
0x14 RXCYCLCNT_LO32 The lower 32-bit of the counter that keeps track of the total number of clock cycles required by the traffic monitor to receive the expected number of packets. RO 0x0
0x18 RXCYCLCNT_HI32 The upper 32-bit of the counter that keeps track of the total number of clock cycles required by the traffic monitor to receive the expected number of packets. RO 0x0
0x1C RXCTRL_STATUS Monitors the configuration and status register.
  • Bit [0]: Set to 1 to initialize all of the traffic monitor counters.
  • Bit [1]: Reserved.
  • Bit [2]: When set to 1, indicates that the traffic monitor has received the total number of expected packets. This bit is a read-only bit.
  • Bits [31:3]: Reserved.
 RW 0x0
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