AN 744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices

ID 683785
Date 5/13/2016
Public

1.9. Configuration Registers

You can access the configuration registers of the designs and their components through the Avalon-MM interface. All registers are 32 bits wide.

Table 8.  Register Map
Byte Offset Component
0x00_0000 Client Logic
0x01_0000 Master ToD
0x02_0000 Channel 0—Triple-Speed Ethernet IP core
0x02_0600 Channel 0—Slave ToD
0x03_0000 Channel 1—Triple-Speed Ethernet IP core
0x03_0600 Channel 1—Slave ToD
0x04_0000 Channel 2—Triple-Speed Ethernet IP core
0x04_0600 Channel 2—Slave ToD
... and so forth up until Channel 9 ... and so forth.

Registers of the Triple-Speed Ethernet IP Core

You can access the register space of the MAC and PCS functions via the Avalon-MM interface of the Triple-Speed Ethernet IP. Because the reference designs used the Qsys tool to instantiate this IP core, the register space is accessed using byte addressing. The Triple-Speed Ethernet MegaCore Function User Guide lists the registers in dword offsets for the MAC registers; word offsets for PCS registers. The MAC registers are 32 bits wide. The PCS registers, however, are 16 bits wide. The 16-bit PCS register occupies the lower 16 bits and the remaining 16 bits are initialized to 0.

The examples below show how byte offsets are derived for both the MAC and PCS registers.

Example 1—accesing the command_config register of the MAC.

Dword offset of the command_config register = 0x02.

Byte offset of the command_config register = (0x02 x 4) = 0x08.

Example 2—accessing the if_mode register of the PCS function.

Word offset of the if_mode register = 0x14.

Dword offset of the if_mode register = 0x80 + 0x14 = 0x94.

Byte offset of the if_mode register = 0x94 x 4 = 0x250.

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