AN 744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices

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ID 683785
Date 5/13/2016
Public
Document Table of Contents
Document Table of Contents x
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices x
1.1. Block Diagrams 1.2. Design Components 1.3. Design Parameters 1.4. Hardware and Software Requirements 1.5. Using the Reference Design 1.6. Upgrading the Components 1.7. Testbench 1.8. Interface Signals 1.9. Configuration Registers 1.10. Document Revision History
1.7. Testbench x
1.7.1. Testbench Files 1.7.2. Simulating the Testbench 1.7.3. Test Case: Design With the IEEE 1588v2 Feature 1.7.4. Test Case: Design Without the IEEE 1588v2 Feature
1.8. Interface Signals x
1.8.1. Packet Classifier Interface Signals 1.8.2. ToD Interface Signals
1.9. Configuration Registers x
1.9.1. ToD Registers 1.9.2. Packet Generator Registers 1.9.3. Traffic Monitor Registers
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices

1.9.2. Packet Generator Registers

The packet generator is a sub-block of the traffic controller and the traffic monitor.

Table 10.  Packet Generator Register Map
Byte Offset Name Description Access Reset Value
0x00 NUMPKTS The total number of Ethernet packets that the traffic generator generates and transmits to the design components. RW 0x0
0x04 RANDOMLENGTH Enables random packet length up to the value of the PKTLENGTH register.
  • 0x00: Fixed length.
  • 0x01: Random length.
 RW 0x0
0x08 RANDOMPAYLOAD Enables random contents of the payload.
  • 0x00: Incremental.
  • 0x01: Random.
 RW 0x0
0x0C START Start the generation of the Ethernet traffic by writing 0x01 to this register. RW 0x0
0x10 STOP Stops the generation of the Ethernet traffic by writing 0x01 to this register. RW 0x0
0x14 MACSA0 The lower 32 bits of the source address. RW 0x0
0x18 MACSA1 The upper 16 bits of the source address. The remaining 16 bits are not used. RW 0x0
0x1C MACDA0 The lower 32 bits of the destination address. RW 0x0
0x20 MACDA1 The upper 16 bits of the source address. The remaining 16 bits are not used. RW 0x0
0x24 TXPKTCNT The number of packets that the traffic generator transmitted. Read this register when the traffic generator is not active, for example, when the testing has completed. RO 0x0
0x34 PKTLENGTH When random-sized packets are enabled, this register specifies the maximum payload length. Otherwise, it specifies the length of the packet to be generated. RW 0x0
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