The Intel® Stratix® 10 E-Tile PCB design guidelines provided in this document are intended to supplement existing Application Notes on PCB design, and not to provide any contradictory information. Intel recommends that you also read the prerequisite Application Notes listed below:
- AN 766: Intel Stratix 10 Devices, High Speed Signal Interface Layout Design Guideline
- Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission
- PCB Breakout Routing for High-Density Serial Channel Designs Beyond 10 Gbps
- PCB Stackup Design considerations for Intel FPGAs
Note that these design guidelines are not tied to any specific platform, which means:
- These design guidelines do not give specific design parameter values. They only provide examples to illustrate the Signal Integrity (SI) design methodology.
- You have the freedom to choose the optimized materials, stackups, and other elements based on your application needs.
Signal integrity simulations are recommended for the E-Tile platform channel design. You must understand the key points below to reach your simulation targets and achieve an optimal design:
- The design margin for E-Tile channels running at 56 Gbps is much smaller than the margin in the 28 Gbps generation due to the additional -9.5 dB intrinsic loss (1/3 NRZ amplitude).
- Industrial standard organizations like IEEE802.3 already specify the channel checking method Channel Operating Margin (COM) for pass/fail criteria.
- Intel provides the IBIS-AMI model and its user guide for SI simulations with the E-Tile silicon's electrical behavior in your own application systems.
The application note uses 56 Gbps to describe data rates in general because of the baseline established in the Common Electrical Interface (CEI). However, the actual data rate can be up to 57.8 Gbps.