AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines

ID 683262
Date 3/12/2019
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2.3.4. PCB Pre-Layout Simulation Phase

Pre-layout simulation is the preliminary phase of the PCB design. This link simulation models the channel on the PCB, and it must cover the items below:
  • Channel impedance corner sweep
  • Channel length/loss sweep
  • You may need to adjust the materials and stackup if the Channel Operating Margin (COM) simulation fails.
  • Record the optimized TX EQ from the COM simulation.

COM (Channel Operating Margin - IEEE802.3cd/bs)

COM is initially published in IEEE802.3cd.

  • Normative channel compliance is through COM computation with specified margin.
  • IEEE802.3cd/bs spec and COM are not fully finalized yet as of this document's publish date.
  • IEEE802.3cd/bs compliance check for the channels is mandatory. It is a fast way to check the compliance of the channels with scattering parameters or S-parameters in touchstone format.
  • The optimized TX FFE c(-2), c(-1), and c(1) may be used to assist in the IBIS-AMI simulation as a “starting point” for TX EQ settings based on the conversion table to be made available in the E-Tile IBIS-AMI model user guide (if the E-tile TX FIR starting point table or RX equalization alone cannot achieve the desired BER target).
  • COM tool is available in the Intel Advanced Link Analyzer (formerly JNEye) for you to test your channels.