AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines

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ID 683262
Date 3/12/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Platform Design Strategy for 56G PAM4 Channels 3. Document Revision History for AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines
2. Platform Design Strategy for 56G PAM4 Channels x
2.1. Intel® Stratix® 10 E-Tile Transceiver Channel Usage Mode 2.2. Intel® Stratix® 10 E-Tile Signaling - PAM4 vs. NRZ (PAM2) 2.3. PCB Design Flow
2.3. PCB Design Flow x
2.3.1. Design Target at 56 Gbps PAM4 Standard 2.3.2. PCB Materials and Stackup Design 2.3.3. FPGA PCB Design 2.3.4. PCB Pre-Layout Simulation Phase 2.3.5. PCB Post-Layout Simulation Phase
2.3.2. PCB Materials and Stackup Design x
2.3.2.1. Insertion Loss 2.3.2.2. Return Loss 2.3.2.3. Package Loss and Crosstalk 2.3.2.4. PCB Via Design 2.3.2.5. PCB Connector 2.3.2.6. Cable Usage in PCB Design
2.3.3. FPGA PCB Design x
2.3.3.1. FPGA PCB Breakout Design and Reference 2.3.3.2. P/N De-skew Strategy on Differential Pairs 2.3.3.3. Crosstalk - NEXT and FEXT in Differential Pairs
1. Introduction
2. Platform Design Strategy for 56G PAM4 Channels
3. Document Revision History for AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines

2.3.2.2. Return Loss

You must optimize the PCB trace impedance to achieve a better return loss or less signal reflection. Factors that determine the PCB impedance Z0 value for a better RL performance are:

  • Elements in the end-to-end channels:
    • Device packages
    • PCB vias
    • Connectors
    • Cables
    • DC block caps (if they exist)
  • PCB stackup and the dielectric and copper materials

Picking the PCB impedance Z0 that gives the minimum impedance fluctuation (discontinuity) with all other elements of the channel is the key for transferring the signal from one end of the channel to the other while minimizing the signal reflection.

The following figure shows an example of PCB trace impedance optimization. From the blue to red performance curves (insertion loss, return loss and time domain reflectometry (TDR) at both ends), it appears that a reduction in the impedance fluctuation eventually leads to a return loss improvement.

Figure 7. Example of PCB Trace Impedance Optimization
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