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1.1. 25G Intel® FPGA IP Ethernet v20.1.0
1.2. 25G Ethernet Intel® FPGA IP v20.0.0
1.3. 25G Ethernet Intel® FPGA IP v19.5.0
1.4. 25G Ethernet Intel® FPGA IP v19.4.1
1.5. 25G Ethernet Intel® FPGA IP v19.4.0
1.6. 25G Ethernet Intel® FPGA IP v19.3.0
1.7. 25G Ethernet Intel® FPGA IP v19.2.0
1.8. 25G Ethernet Intel® FPGA IP v19.1
1.9. 25G Ethernet Intel® FPGA IP v18.1
1.10. 25G Ethernet Intel® FPGA IP v18.0
1.11. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives
1.12. 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
2.1. 25G Ethernet Intel® FPGA IP v19.4.1
2.2. 25G Ethernet Intel® FPGA IP v19.4.0
2.3. 25G Ethernet Intel® FPGA IP v19.1
2.4. 25G Ethernet IP Core v17.0
2.5. 25G Ethernet IP Core v16.1
2.6. 25G Ethernet Intel® Arria® 10 FPGA IP User Guide Archive
2.7. 25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide Archives
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1. 25G Ethernet Intel FPGA IP Release Notes ( Intel Agilex® 7 Devices)
Intel® FPGA IP versions match the Intel® Quartus® Prime Design Suite software versions until v19.1. Starting in Intel® Quartus® Prime Design Suite software version 19.2, Intel® FPGA IP has a new versioning scheme.
The Intel® FPGA IP version (X.Y.Z) number can change with each Intel® Quartus® Prime software version. A change in:
- X indicates a major revision of the IP. If you update the Intel® Quartus® Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.