25G Ethernet Intel® FPGA IP Release Notes

ID 683067
Date 8/01/2023

1.5. 25G Ethernet Intel® FPGA IP v19.4.0

Table 5.  v19.4.0 2019.12.16
Intel® Quartus® Prime Version Description Impact
19.4 rx_am_lock behavior change:
  • In previous versions of the 25G Ethernet Intel® FPGA IP, the rx_am_lock signal behaves the same as rx_block_lock across all variants.
  • In this version, for RSFEC enabled variants of the IP, rx_am_lock now asserts when alignment lock is achieved. For non-RSFEC enabled variants, rx_am_lock still behaves the same as rx_block_lock.
The interface signal, rx_am_lock, behaves differently from the previous versions for the RSFEC-enabled variants.
Updated the RX MAC Start of Packet:
  • In previous versions, the RX MAC only checks for a START character to determine the start of a packet.
  • In this version, the RX MAC now checks for incoming packets for Start of Frame Delimiter (SFD), in addition to the START character by default.
  • If the preamble pass-through mode is enabled, the MAC checks only for the START character to allow for custom preamble.
Added a new register to enable preamble checking:
  • In the RX MAC registers, the register at offset 0x50A [4] can be written to 1 to enable the preamble checking. This register is a "don't care" when the preamble pass-through is enabled.