25G Ethernet Intel® FPGA IP Release Notes

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ID 683067
Date 8/01/2023
Public
Document Table of Contents
Document Table of Contents x
1. 25G Ethernet Intel® FPGA IP Release Notes (Intel Stratix 10 Devices) 2. 25G Ethernet Intel® FPGA IP Release Notes (Intel Arria 10 Devices)
1. 25G Ethernet Intel® FPGA IP Release Notes (Intel Stratix 10 Devices) x
1.1. 25G Intel® FPGA IP Ethernet v20.1.0 1.2. 25G Ethernet Intel® FPGA IP v20.0.0 1.3. 25G Ethernet Intel® FPGA IP v19.5.0 1.4. 25G Ethernet Intel® FPGA IP v19.4.1 1.5. 25G Ethernet Intel® FPGA IP v19.4.0 1.6. 25G Ethernet Intel® FPGA IP v19.3.0 1.7. 25G Ethernet Intel® FPGA IP v19.2.0 1.8. 25G Ethernet Intel® FPGA IP v19.1 1.9. 25G Ethernet Intel® FPGA IP v18.1 1.10. 25G Ethernet Intel® FPGA IP v18.0 1.11. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives 1.12. 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
2. 25G Ethernet Intel® FPGA IP Release Notes (Intel Arria 10 Devices) x
2.1. 25G Ethernet Intel® FPGA IP v19.4.1 2.2. 25G Ethernet Intel® FPGA IP v19.4.0 2.3. 25G Ethernet Intel® FPGA IP v19.1 2.4. 25G Ethernet IP Core v17.0 2.5. 25G Ethernet IP Core v16.1 2.6. 25G Ethernet Intel® Arria® 10 FPGA IP User Guide Archive 2.7. 25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide Archives
1. 25G Ethernet Intel® FPGA IP Release Notes (Intel Stratix 10 Devices)
2. 25G Ethernet Intel® FPGA IP Release Notes (Intel Arria 10 Devices)

1.5. 25G Ethernet Intel® FPGA IP v19.4.0

Table 5.  v19.4.0 2019.12.16
Intel® Quartus® Prime Version Description Impact
19.4 rx_am_lock behavior change:
  • In previous versions of the 25G Ethernet Intel® FPGA IP, the rx_am_lock signal behaves the same as rx_block_lock across all variants.
  • In this version, for RSFEC enabled variants of the IP, rx_am_lock now asserts when alignment lock is achieved. For non-RSFEC enabled variants, rx_am_lock still behaves the same as rx_block_lock.
The interface signal, rx_am_lock, behaves differently from the previous versions for the RSFEC-enabled variants.
Updated the RX MAC Start of Packet:
  • In previous versions, the RX MAC only checks for a START character to determine the start of a packet.
  • In this version, the RX MAC now checks for incoming packets for Start of Frame Delimiter (SFD), in addition to the START character by default.
  • If the preamble pass-through mode is enabled, the MAC checks only for the START character to allow for custom preamble.
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Added a new register to enable preamble checking:
  • In the RX MAC registers, the register at offset 0x50A [4] can be written to 1 to enable the preamble checking. This register is a "don't care" when the preamble pass-through is enabled.
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