25G Ethernet Intel® FPGA IP Release Notes

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ID 683067
Date 8/01/2023
Public
Document Table of Contents
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1. 25G Ethernet Intel® FPGA IP Release Notes (Intel Stratix 10 Devices) 2. 25G Ethernet Intel® FPGA IP Release Notes (Intel Arria 10 Devices)
1. 25G Ethernet Intel® FPGA IP Release Notes (Intel Stratix 10 Devices) x
1.1. 25G Intel® FPGA IP Ethernet v20.1.0 1.2. 25G Ethernet Intel® FPGA IP v20.0.0 1.3. 25G Ethernet Intel® FPGA IP v19.5.0 1.4. 25G Ethernet Intel® FPGA IP v19.4.1 1.5. 25G Ethernet Intel® FPGA IP v19.4.0 1.6. 25G Ethernet Intel® FPGA IP v19.3.0 1.7. 25G Ethernet Intel® FPGA IP v19.2.0 1.8. 25G Ethernet Intel® FPGA IP v19.1 1.9. 25G Ethernet Intel® FPGA IP v18.1 1.10. 25G Ethernet Intel® FPGA IP v18.0 1.11. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives 1.12. 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
2. 25G Ethernet Intel® FPGA IP Release Notes (Intel Arria 10 Devices) x
2.1. 25G Ethernet Intel® FPGA IP v19.4.1 2.2. 25G Ethernet Intel® FPGA IP v19.4.0 2.3. 25G Ethernet Intel® FPGA IP v19.1 2.4. 25G Ethernet IP Core v17.0 2.5. 25G Ethernet IP Core v16.1 2.6. 25G Ethernet Intel® Arria® 10 FPGA IP User Guide Archive 2.7. 25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide Archives
1. 25G Ethernet Intel® FPGA IP Release Notes (Intel Stratix 10 Devices)
2. 25G Ethernet Intel® FPGA IP Release Notes (Intel Arria 10 Devices)

2.3. 25G Ethernet Intel® FPGA IP v19.1

Table 13.  v19.1 April 2019
Description Impact
Renamed the Enable Altera Debug Master Endpoint (ADME) parameter to Enable Native PHY Debug Master Endpoint (NPDME) as per Intel® rebranding in the Intel® Quartus® Prime Pro Edition software. The Intel® Quartus® Prime Standard Edition software still uses Enable Altera Debug Master Endpoint (ADME). —
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