Device Configuration - Support Center

You will find information on how to select, design, and implement configuration schemes and features. There are also guidelines on how to bring up your system and debug the configuration links. This page is organized into categories that align with a configuration system design flow from start to finish.

Get support resources for Intel Agilex® 7, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 devices from the pages below. For other devices, search from the following links: Documentation, Training Courses, Intel® FPGA Quick Videos, Intel® FPGA Design Examples, and FPGA Knowledge Base.

1. Device Specific Configuration Details

Table 1 - Configuration Schemes and Features Overview

Device Family	Configuration Schemes				Configuration Features
	Scheme	Data Width	Max Clock Rate	Max Data Rate	Design Security	Partial Reconfiguration (2)	Remote System Update	Single Event Upsets	Configuration via Protocol
Intel Agilex® 7	Avalon® Streaming	32 bits	125 MHz	4000 Mbps	√	√	Parallel Flash Loader II IP core	√	N/A
		16 bits	125 MHz	2000 Mbps	√	√
		8 bits	125 MHz	1000 Mbps	√	√
	Active Serial (AS)	4 bits	166⁽¹⁾ MHz	664 Mbps	√	√	√	√	√
	JTAG	1 bit	30 MHz	30 Mbps	√	√	N/A	√	N/A
Intel® Stratix® 10	Avalon®-ST	32 bits	125 MHz	4000 Mbps	√	√	Parallel Flash Loader II IP core	√	N/A
		16 bits	125 MHz	2000 Mbps	√	√
		8 bits	125 MHz	1000 Mbps	√	√
	Active Serial (AS)	4 bits	125⁽¹⁾MHz	500 Mbps	√	√	√	√	√
	JTAG	1 bit	30 MHz	30 Mbps	√	√	N/A	√	N/A
Intel® Arria® 10	Configuration via HPS	32 bits	100 MHz	3200 Mbps	√	√	via HPS	√	N/A
	Configuration via HPS	16 bits	100 MHz	1600 Mbps	√	√	via HPS	√	N/A
	Fast Passive Parallel (FPP)	32 bits	100 MHz	3200 Mbps	√	√	Parallel Flash Loader IP core	√	N/A
		16 bits	100 MHz	1600 Mbps	√
		8 bits	100 MHz	800 Mbps	√
	Active Serial (AS)	4 bits	100 MHz	400 Mbps	√	√⁽³⁾	√	√	√
	Active Serial (AS)	1 bit	100 MHz	100 Mbps	√	√⁽³⁾	√	√	√
	Passive Serial (PS)	1 bit	100 MHz	100 Mbps	√	√⁽³⁾	Parallel Flash Loader IP core	√	N/A
	JTAG	1 bit	33 MHz	33 Mbps		√⁽³⁾	N/A	√	N/A
Intel® Cyclone® 10 GX	Fast Passive Parallel (FPP)	32 bits	100 MHz	3200 Mbps	√	√	Parallel Flash Loader IP core	√	N/A
		16 bits	100 MHz	1600 Mbps	√
		8 bits	100 MHz	800 Mbps	√
	Active Serial (AS)	4 bit	100 MHz	400 Mbps	√	√⁽³⁾	√	√	√
	Active Serial (AS)	1 bits	100 MHz	100 Mbps	√	√⁽³⁾	√	√	√
	Passive Serial (PS)	1 bit	100 MHz	100 Mbps	√	√⁽³⁾	Parallel Flash Loader IP core	√	N/A
	JTAG	1 bit	33 MHz	33 Mbps	N/A	√⁽³⁾	N/A	√	N/A
Intel® Cyclone® 10 LP	Fast Passive Parallel (FPP)	8 bits	66⁽⁴⁾/100⁽⁶⁾ MHz	528⁽⁴⁾/800⁽⁶⁾ Mbps	N/A	N/A	Parallel Flash Loader IP core	√	N/A
	Passive Serial (PS)	1 bit	66⁽⁴⁾/133⁽⁵⁾ MHz	66⁽⁴⁾/133⁽⁵⁾ Mbps	N/A	N/A	Parallel Flash Loader IP core	√	N/A
	Active Serial (AS)	1 bit	40 MHz	40 Mbps	N/A	N/A	√	√	N/A
	JTAG	1 bit	25 MHz	25 Mbps	N/A	N/A	N/A	√	N/A

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The maximum clock rate when using OSC_CLK_1 as configuration clock source. The maximum clock rate reduces if you use the internal oscillator as the configuration clock source, during SmartVID operation, or when the device is in user mode.
You can perform partial reconfiguration after the device is fully configured. For more information, refer to the Partial Reconfiguration User Guide.
Partial configuration can be performed only when it is configured as internal host.
Supply voltage for internal logic, VCCINT = 1.0 V.
Supply voltage for internal logic, VCCINT = 1.2 V.
Supply voltage for internal logic, VCCINT = 1.2 V. Cyclone 10 LP 1.2 V core voltage devices support 133 MHz DCLK fMAX for 10CL006, 10CL010, 10CL016, 10CL025, and 10CL040 only.

2. Configuration Schemes and IP

Configuration User Guides

Intel Agilex® 7 Devices

Intel Agilex® 7 Configuration User Guide

Intel Stratix 10 Devices

Intel Stratix 10 Configuration User Guide

Configuration via HPS

Configure the FPGA portion of the SoC device by utilizing Hard Processor System (HPS)

Intel Agilex® 7 Devices

Intel Agilex® 7 Hard Processor System Technical Reference Manual

Intel Stratix 10 Devices

Intel Arria 10 Devices

Fast Passive Parallel

Intel Arria 10 Devices

Intel Arria 10 Core Fabric and General Purpose I/Os Handbook

Intel Cyclone 10 GX Devices

Intel Cyclone 10 GX Core Fabric and General Purpose I/Os Handbook

Intel Cyclone 10 LP Devices

Intel Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook

Additional Resources:

Intel® FPGA Parallel Flash Loader IP Core User Guide

Active Serial

Intel Agilex® 7 Devices

Intel Agilex® 7 Configuration User Guide

Intel Stratix 10 Devices

Intel Stratix 10 Configuration User Guide

Intel Arria 10 Devices

Intel Arria 10 Core Fabric and General Purpose I/Os Handbook

Intel Cyclone 10 GX Devices

Intel Cyclone 10 GX Core Fabric and General Purpose I/Os Handbook

Intel Cyclone 10 LP Devices

Intel Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook

Additional Resources:

AN 370: Using the Intel FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software

AN 418: SRunner: An Embedded Solution for Serial Configuration Device Programming

Passive Serial

Intel Arria 10 GX Devices

Intel Arria 10 Core Fabric and General Purpose I/Os Handbook

Intel Cyclone 10 GX Devices

Intel Cyclone 10 GX Core Fabric and General Purpose I/Os Handbook

Intel Cyclone 10 LP Devices

Intel Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook

Additional Resources:

Intel FPGA Parallel Flash Loader IP Core User Guide

JTAG

Intel Agilex® 7 Devices

Intel Stratix 10 Devices

Intel Arria 10 Devices

Intel Arria 10 Core Fabric and General Purpose I/Os Handbook

Intel Cyclone 10 GX Devices

Intel Cyclone 10 GX Core Fabric and General Purpose I/Os Handbook

Intel Cyclone 10 LP Devices

Intel Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook

Additional Resources:

3. Advanced Configuration Features

Device Security

Intel Agilex® 7 Devices

AN 933: Updating Intel Stratix 10 FPGA Firmware

Intel Stratix 10 Devices

Intel Stratix 10 Device Security User Guide

Intel Arria 10 Devices

Intel Arria 10 Core Fabric and General Purpose I/Os Handbook

Intel Cyclone 10 GX Devices

Intel Cyclone 10 GX Core Fabric and General Purpose I/Os Handbook

Additional Resources:

AN 556: Using the Design Security Features in Intel FPGAs

Partial Reconfiguration

Partial Reconfiguration Support Page

Intel Agilex® 7 Devices

Partial Reconfiguration Solutions IP User Guide

Intel Stratix 10 Devices

Intel® Arria® 10 Devices

Intel® Cyclone®10 GX Devices

Partial Reconfiguration Solutions IP User Guide

Additional Resources:

Remote System Upgrade

Intel Agilex® 7 Devices

Intel Agilex® 7 Configuration User Guide

Intel Stratix 10 Devices

Intel Arria 10 Devices

Intel Arria 10 Core Fabric and General Purpose I/Os Handbook

Intel Cyclone 10 GX Devices

Intel Cyclone 10 GX Core Fabric and General Purpose I/Os Handbook

Intel Cyclone 10 LP Devices

Intel Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook

Additional Resources:

Remote Update Intel FPGA IP Core User Guide

Single Event Upset (SEU) Mitigation

Intel Agilex® 7 Devices

Intel Agilex® 7 SEU Mitigation User Guide

Intel Stratix 10 Devices

Intel Stratix 10 SEU Mitigation User Guide

Intel Arria 10 Devices

Intel Cyclone 10 GX Devices

Intel Cyclone 10 GX Core Fabric and General Purpose I/Os Handbook

Intel Cyclone 10 LP Devices

Intel Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook

Additional Resources:

Configuration via Protocol (CvP)

Configuration via Protocol Support Page

Intel Agilex® 7 Devices

Intel Agilex® 7 Device Configuration via Protocol (CvP) Implementation User Guide

Intel Stratix 10 Devices

Intel Arria 10 Devices

Intel Cyclone 10 GX Devices

Flash Access IP

Intel Agilex® 7 Devices

Intel Stratix 10 Devices

Intel Arria 10 Devices

Intel Cyclone 10 GX Devices

Intel Cyclone 10 LP Devices

Chip ID IP

Intel Agilex® 7 Devices

Intel Stratix 10 Devices

Chip ID Intel FPGA IP Cores User Guide

Intel Arria 10 Devices

Chip ID Intel FPGA IP Cores User Guide

Intel Cyclone 10 GX Devices

Chip ID Intel FPGA IP Cores User Guide

4. Intel® Quartus® Prime Software Design Flow

Table 2 - Device Configuration Setting and Programming Files Generation Flow


1. General Setting
General page of the Device and Pin Options dialog box in the Intel Quartus Prime Software. Specify the device options. These options are independent on the configuration scheme.
2. Configuration Setting
Configuration page of the Device and Pin Options dialog box in the Intel Quartus Prime Software. Specify the Device Configuration scheme, Configuration Device setting and Configuration Pin setting.
3. Programming Files Setting
Programming Files page of the Device and Pin Options dialog box in the Intel Quartus Prime Software. Select the programming file format to generate. Selecting the programming file in this page is optional, user is recommended to use the Convert Programming File or Programming File Generator to convert/generate the type of programming file for the used of selected configuration scheme.
4. Others Optional Advanced Feature Setting
Error Detection CRC, CvP Settings and Partial Reconfiguration page of the Device and Pin Options dialog box in the Intel Quartus Prime Software. Error Detection CRC page - Specify whether error detection is used and the rate at which it is checked. CvP Settings page - Specify the type of CvP settings. Partial Reconfiguration page - Specify Partial Reconfiguration settings.
5. Generate Configuration and Programming Files
Once design compilation is completed, the Convert Programming Files or Programming File Generator is the tool in Intel Quartus Prime Software to convert/generate the type of programming file for selected configuration scheme or configuration feature.

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Where Can I Find Information on Device Configuration Settings and Configuration & Programming Files Generation?

Intel Agilex® 7 Devices

Intel Agilex® 7 Configuration User Guide

Intel Stratix 10 Devices

Intel Stratix 10 Configuration User Guide

Intel Arria 10 Devices

Intel Arria 10 Core Fabric and General Purpose I/Os Handbook

Intel Cyclone 10 GX Devices

Intel Cyclone 10 GX Core Fabric and General Purpose I/Os Handbook

Intel Cyclone 10 LP Devices

Intel Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook

5. Board Design

Where Can I Find Information on Device Configuration Design Guidelines?

Intel Agilex® 7 Devices

AN 886: Intel Agilex® 7 Device Design Guidelines

Intel Stratix 10 Devices

Intel Stratix 10 Device Design Guidelines

Intel Arria 10 Devices

Intel Cyclone 10 GX Devices

Intel® Cyclone® 10 GX Device Design Guidelines

Where Can I Find Information on the Connection Guidelines for Configuration Pin?

Intel Agilex® 7 Devices

Intel Agilex® 7 Device Family Pin Connection Guidelines

Intel Stratix 10 Devices

Intel Stratix® 10 Device Family Pin Connection Guidelines

Intel Arria 10 Devices

Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines

Intel Cyclone 10 GX Devices

Intel Cyclone 10 GX Device Family Pin Connection Guidelines

Intel Cyclone 10 LP Devices

Intel Cyclone 10 LP Device Family Pin Connection Guidelines

Where Can I Find Information on Configuration Specifications?

The configuration specification in the device datasheet specifies the following specifications:

Timing specifications for configuration control pins
Timing/Performance specifications for each of the supported configuration scheme
Configuration bit stream sizes
Configuration time estimation for each of the supported configuration scheme

Intel Agilex® 7 Devices

Intel Agilex® 7 Device Datasheet

Intel Stratix 10 Devices

Intel Stratix 10 Device Datasheet

Intel Arria 10 Devices

Intel Cyclone 10 GX Devices

Intel Cyclone 10 LP Devices

6. Debug

Configuration debugger tool helps you debug programming and configuration issues. This tool is supported in Intel® Quartus® Prime Pro Edition Programmer version 21.3 onwards.

AN 955: Programmer’s Configuration Debugger Tool

FPGA Configuration Troubleshooter

Intel Agilex® 7 and Intel Stratix 10 FPGA System Console Debugging Tool Using JTAG

AN 936: Executing SDM Commands via JTAG Interface

Intel Stratix 10 FPGA SDM Debug Toolkit helps you debug your configuration issues.

It is available in Intel Quartus Prime Pro Edition software v18.1 and onwards.

Searching a tool to debug configuration failures / design security / error detection cyclic redundancy check (CRC) on Intel® Arria® 10 devices?

To get this configuration diagnostic tool, please contact your Intel® sales representative.

You can use this troubleshooter or fault tree analysis to identify possible configuration failure causes.

Knowledge Base Solution

Go to Knowledge Base, enter the keywords of the issue you face to find for the solution.

Configuration Devices

Table 3 - Intel® FPGA Configuration Devices

Configuration Device Family	Capacity	Package	Voltage	FPGA Product Family Compatibility
EPCQ-A†	4 Mb - 32 Mb	8-pin SOIC	3.3 V	Compatible with Stratix® V, Arria® V, Cyclone® V, Intel® Cyclone® 10 LP and earlier FPGA families.
EPCQ-A†	64 Mb - 128 Mb	16-pin SOIC	3.3 V	Compatible with Stratix® V, Arria® V, Cyclone® V, Intel® Cyclone® 10 LP and earlier FPGA families.
Notes: † EPCQ-A family is supported from Intel® Quartus® Prime Standard Edition Software v17.1 onwards. For product family support for legacy families not included in version 17.1 file a Service Request. See also Configuration Devices.

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Table 4 - Intel Supported Third Party Configuration Devices

Intel FPGA	Vendor	Part Number		Byte addressing	Dummy Clock Settings		Permanent Quad-Enabled flash?	Support Category
		Prefix	Suffix		ASx1	ASx4
Intel Agilex	Micron	MT25QU128	ABA8E12-0AAT	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Intel Tested and Supported
		MT25QU256	ABA8E12-0AAT
		MT25QU512	ABB8E12-0AAT
		MT25QU01G	BBB8E12-0AAT
		MT25QU02G	CBB8E12-0AAT
	Macronix⁽¹⁰⁾	MX25U12835F	XDI-10G	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Intel Tested and Supported
		MX25U25643G	XDI00					Known to Work⁽¹³⁾
		MX25U25645G	XDI00					Intel Tested and Supported
		MX25U51245G	XDI00
		MX66U1G45G	XDI00
		MX66U2G45G	XRI00
	ISSI	IS25WP256E	-RHLE	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		IS25WP512M	-RHLE
		IS25WP01G	-RHLE⁽²²⁾
	Gigadevice	GD25LB512ME	BFRY⁽²³⁾	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		GD25LT512ME	BIRY⁽²³⁾
		GD55LB01GE	BIRY⁽²³⁾
		GD55LT01GE	BFRY⁽²³⁾
		GD55LB02GE	BIR⁽²³⁾
	Winbond	W25Q512NW	FIA⁽²³⁾	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
Intel Stratix 10	Micron	MT25QU128	ABA8ESF-0SIT	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Known to Work⁽¹¹⁾
		MT25QU256	ABA8E12-1SIT
		MT25QU512	ABB8ESF-0SIT
		MT25QU01G	BBB8ESF-0SIT					Intel Tested and Supported
		MT25QU02G	CBB8E12-0SIT					Known to Work⁽¹¹⁾
	Macronix⁽¹⁰⁾	MX25U12835F	MI-100	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Known to Work⁽¹¹⁾
		MX25U25643G	XDI00					Known to Work⁽¹³⁾
		MX25U25645G	XDI00
		MX25U51245G	XDI00
		MX66U51235F	XDI-10G					Known to Work⁽¹¹⁾
		MX66U1G45G	XDI00					Known to Work⁽¹¹⁾
		MX66U2G45G	XRI00					Intel Tested and Supported
	ISSI	IS25WP256E	-RHLE	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		IS25WP512M	-RHLE
		IS25WP01G	-RILE⁽²²⁾
	Gigadevice	GD25LB512ME	BFRY⁽²³⁾	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		GD25LT512ME	BIRY⁽²³⁾
		GD55LB01GE	BIRY⁽²³⁾
		GD55LT01GE	BFRY⁽²³⁾
		GD55LB02GE	BIR⁽²³⁾
	Winbond	W25Q512NW	FIA⁽²³⁾	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
Intel Arria 10, Intel Cyclone 10 GX	Micron	MT25QU256	ABA8E12-1SIT	4-byte⁽⁴⁾	10⁽⁴⁾	10⁽⁴⁾	No⁽⁶⁾	Known to Work⁽¹¹⁾
		MT25QU512	ABB8ESF-0SIT					Known to Work⁽¹³⁾
		MT25QU512	ABB8E12-0SIT					Known to Work⁽¹²⁾
		MT25QL512	ABA8ESF-0SIT
		MT25QL512	ABB8ESF-0SIT
		MT25QU01G	BBB8ESF-0SIT					Known to Work⁽¹³⁾
		MT25QU01G	BBB8E12-0SIT					Known to Work⁽¹²⁾
		MT25QU01G	BBA8E12-0SIT					Known to Work⁽¹²⁾
		MT25QU02G	CBB8E12-0SIT					Known to Work⁽¹³⁾
	Macronix	MX25U256	45GXDI54⁽³⁾	4-byte⁽⁵⁾	10⁽⁵⁾	10⁽⁵⁾	Yes⁽⁶⁾	Known to Work⁽¹¹⁾
		MX25U512	45GXDI54⁽³⁾	4-byte⁽⁵⁾	10⁽⁵⁾	10⁽⁵⁾	Yes⁽⁶⁾	Known to Work⁽¹¹⁾
		MX25U512	45GMI00⁽¹⁸⁾	3-byte⁽¹⁾	8⁽¹⁾	6⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹²⁾
		MX66L512	35FMI-10G⁽¹⁹⁾	3-byte⁽¹⁾	8⁽¹⁾	6⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹²⁾
		MX66U1G	45GXDI54⁽³⁾	4-byte⁽⁵⁾	10⁽⁵⁾	10⁽⁵⁾	Yes⁽⁶⁾	Known to Work⁽¹¹⁾
		MX66L1G	45GMI-10G⁽²⁰⁾	3-byte⁽¹⁾	8⁽¹⁾	6⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹²⁾
		MX66U2G	45GXRI54⁽³⁾	4-byte⁽⁵⁾	10⁽⁵⁾	10⁽⁵⁾	Yes⁽⁶⁾	Known to Work⁽¹¹⁾
	Cypress/Infineon	S25FS512	SDSBHV210	3-byte⁽¹⁾⁽²⁾	8⁽¹⁾	6⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹²⁾
		S25FL512	AGMFI011
		S70FL01G	SAGMFI011
Cyclone V, Cyclone V SoC, Arria V, Arria V SoC, Stratix V	Micron	MT25QL128	ABA8ESF-0SIT	3-byte⁽¹⁾	12⁽⁴⁾	12⁽⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		MT25QU128	ABA8ESF-0SIT	3-byte⁽¹⁾	10⁽¹⁾	10⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹²⁾
		MT25QU256	ABA8ESF-0SIT	3-byte⁽¹⁾	10⁽¹⁾	10⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹²⁾
		MT25QL256	ABA8ESF-0SIT	4-byte⁽⁴⁾	4⁽⁴⁾	10⁽⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		MT25QL512	ABB8ESF-0SIT	4-byte⁽⁴⁾	4⁽⁴⁾	10⁽⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		MT25QL512	ABA8ESF-0SIT	3-byte⁽¹⁾	10⁽¹⁾	10⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹²⁾
		MT25QL01G	BBB8ESF-0SIT	4-byte⁽⁴⁾	4⁽⁴⁾	10⁽⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		MT25QL02G	CBB8E12-0SIT	4-byte⁽⁴⁾	4⁽⁴⁾	10⁽⁴⁾	No⁽⁶⁾	Known to Work⁽¹¹⁾
	Macronix	MX25L128	33FMI-10G⁽¹⁵⁾	3-byte⁽¹⁾⁽²⁾	8⁽¹⁾	6⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		MX25L256	45GMI-08G⁽¹⁶⁾					Known to Work⁽¹³⁾
		MX25L256	35FMI-10G⁽¹⁶⁾					Known to Work⁽¹²⁾
		MX25L512	45GMI-08G⁽¹⁵⁾					Known to Work⁽¹³⁾
		MX66L512	35FMI-10G⁽¹⁵⁾					Known to Work⁽¹²⁾
		MX25U512	45GMI00⁽¹⁶⁾
		MX25U512	45GXDI00⁽¹⁶⁾
		MX66L1G	45GMI-10G⁽¹⁶⁾
		MX66U2G	45GXR100⁽¹⁵⁾
	Cypress/Infineon	S25FL128	SAGMFI000	3-byte⁽¹⁾⁽²⁾	8⁽¹⁾	6⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		S25FL256	SAGMFI000
		S25FL512	SAGMFI010
		S25FL512	SAGMFIG11					Known to Work⁽¹²⁾
		S70FL01G	SAGMFI011⁽¹⁷⁾					Known to Work⁽¹²⁾
	Gigadevice	GD25Q127	CFIG⁽¹⁵⁾	3-byte⁽¹⁾⁽²⁾	8⁽¹⁾	4⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹²⁾
	Gigadevice	GD25Q256	DFIG⁽¹⁵⁾	3-byte⁽¹⁾⁽²⁾	8⁽¹⁾	4⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹²⁾
Cyclone 10 LP	Micron	MT25QL128	ABA8ESF-0SIT	3-byte⁽¹⁾⁽²⁾	8⁽¹⁾	N/A	No⁽⁶⁾	Known to Work⁽¹¹⁾
		MT25QL256	ABA8ESF-0SIT
		MT25QL512	ABB8ESF-0SIT
		MT25QL01G	BBB8ESF-0SIT
		MT25QL02G	CBB8E12-0SIT
	Macronix	MX25L128	33FMI-10G	3-byte⁽¹⁾⁽²⁾	8⁽¹⁾	N/A	No⁽⁶⁾	Known to Work⁽¹¹⁾
		MX25L256	45GMI-08G
		MX25L512	45GMI-08G
	Cypress/Infineon	S25FL128	SAGMFI000	3-byte⁽¹⁾⁽²⁾	8⁽¹⁾	N/A	No⁽⁶⁾	Known to Work⁽¹¹⁾
		S25FL256	SAGMFI000
		S25FL512	SAGMFI0I0
Table 3 shows the criteria of third party configuration devices supported by Intel Quartus Convert Programming File Tools/Programming File Generator and Quartus Programmer version 21.3 Pro Edition and 20.1 Standard Edition onwards. Intel tested and supported: These devices receive regression testing with Intel FPGA tools and their use is fully supported by Intel FPGA Technical Support. Known to work: These devices are supported by Intel Quartus Convert Programming File Tools or Programming File Generator Tools and Quartus Programmer version 21.3 Pro Edition or 20.1 Standard Edition or newer versions. For devices not explicitly listed in the Configuration Device list in Programming File Generator Tools, you can define a custom device using the available menu options.

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Notes:

Using the default setting of the configuration devices.
When performing remote system upgrade, the start address of the images must be set within first 128 Mb.
Intel Arria 10 and Intel Cyclone 10 GX devices support only Macronix configuration devices with part number MX25U25645GXDI54, MX25U51245GXDI54, MX66U1G45GXDI54, MX66U2G45GXRI54.
Intel Quartus Programmer set the non-volatile configuration register during programming operation. User need to set the register manually if using a third-party programmer.
The configuration devices is permanent to this value, user do not have the options to change this setting.
Intel Quartus Programmer issues command to enable quad mode
These configuration devices are not supported by legacy ASMI Parallel I Intel FPGA IP core and ASMI Parallel II Intel FPGA IP core. For new design, please refer to Generic Serial Flash Interface Intel FPGA IP core.
AS x 1 - Active serial configuration support 1 bit data width
AS x 4 - Active serial configuration scheme support 4 bit data width
Intel Stratix 10 and Intel Agilex® 7 devices do not support Macronix configuration devices with part number MX25U25645GXDI54, MX25U51245GXDI54, MX66U1G45GXDI54 and MX66U2G45GXRI54.
Tested with FPGA configuration.
Tested with HPS.
Tested with FPGA configuration and HPS.
FPGA boot ROM perform normal READ operation to load the firmware which is initial part of the bit stream, after firmware is loaded, it reads the Serial Flash Discovery Parameter(SFDP) table defined by flash vendor to determine the number of dummy clock cycles for performing Quad I/O FAST READ operation to load the rest of the bit stream.
U-Boot updates needed. U-Boot used for flashing.
U-Boot updates needed.
Two chip selects. HPS Flash Programmer and BootROM use only CS0.
U-Boot modifications needed
Programmed with U-Boot
Programmed with modified U-Boot
S70FS01G is incompatible with Intel Arria 10 and Intel Cyclone 10 GX device.
You need to define New Flash Memory Configuration Device based on programming flow template: Device ID=0x9d 0x70 0x1b, Device density=1024Mb, Total device die=1, Programming flow template=Macronix. Refer to add a custom flash device in Generic Flash Programmer User Guide: Intel Quartus Prime Pro Edition.
You need to define New Flash Memory Configuration Device based on programming flow template: Device ID=0x00 0x00 0x00, Device density=512Mb/1024Mb/2048Mb, Total device die=1, Programming flow template=Macronix. Refer to add a custom flash device in Generic Flash Programmer User Guide: Intel Quartus Prime Pro Edition.
You need to define New Flash Memory Configuration Device based on programming flow template: Need to add part to Programmer: Device ID=0x9d 0x70 0x1b, Device density=1024Mb, Total device die=1, Programming flow template=Issi. Refer to add a custom flash device in Generic Flash Programmer User Guide: Intel Quartus Prime Pro Edition.

Design Examples and Reference Designs

Design Examples and Reference Designs

Design Store

Intel Agilex® 7 Devices

Intel Stratix 10 Devices

Intel Arria 10 Devices

Intel Cyclone 10 GX Devices

Intel Cyclone 10 LP Devices

Table 5 - Training Courses and Videos

Intel® FPGA Technical Training Catalog

Video Title	Description
Introduction to Configuring Intel FPGAs	Learn the configuration schemes, solutions, features and tools available for configuring Intel FPGAs and programming configuration devices.
Configuration Schemes for Intel FPGAs	Learn the difference between all the configuration schemes that can be used to configure Intel FPGAs.
Configuration for Intel Stratix 10 Devices	Learn the unique configuration features available in the Intel Stratix 10 devices.
Remote System Upgrade in Intel MAX 10 Devices	Learn how to set up and perform a RSU in an Intel MAX 10 device.
Creating Second Stage Bootloader for Intel FPGA SoCs	Learn the flow and tools available to quickly customize and generate the second stage boot software.
Secure Boot with Intel Arria 10 SoC FPGAs	Learn to generate and program Intel® Arria® 10 SoC FPGAs with and encrypted and/or signed second stage boot image.
Mitigating Single Event Upsets in Intel Arria 10 and Intel Cyclone 10 GX Devices	Learn the features of the Intel® Arria® 10 and Intel Cyclone 10 GX device families that can be used in the designing your own SEU mitigation solution.
SEU Mitigation in Intel FPGA Devices: Hierarchy Tagging	Learn how you can improve your sensitivity processing solution by supplementing single event upset (SEU) mitigation technique with feature called hierarchy tagging.
SEU Mitigation in Intel FPGA Devices: Fault Injection	Learn about Fault Injection IP core and Fault Injection Debugger software to reduce Failure in Time (FIT) rate.
Using the Generic Serial Flash Interface	Learn how to use the Generic Serial Flash Interface Intel FPGA IP Core to program any serial peripheral interface (SPI) type flash device.
SoC Hardware Overview: Flash Controllers and Interface Protocols	Learn about the Hard Processor Subsystem (HPS) found on the Cyclone V, Arria V, and Arria 10 SoCs. The online training includes information about the non-volatile storage controllers and the various interface protocols.
Partial Reconfiguration for Intel FPGA Devices: Introduction & Project Assignments	Partial Reconfiguration Training part 1 of 4. This part of the training introduces you to the PR feature and the general design flow for a PR design. You'll also learn about design partition and Logic Lock region assignments, required assignments for implementing a PR design, and recommendations for how to floorplan a design for PR.
Partial Reconfiguration for Intel FPGA Devices: Design Guidelines & Host Requirements	Partial Reconfiguration Training part 2 of 4. This part of the training discusses the guidelines for creating a PR design, including the creation of a port superset and freeze logic. It also discusses the requirements for a PR host, the logic added to the design's static region or an external device to control PR operations.
Partial Reconfiguration for Intel FPGA Devices: PR Host IP & Implementations	Partial Reconfiguration Training part 3 of 4. This part of the training discusses all of the PR IP included in the Intel Quartus Prime software, including the PR Controller IP, Region Controller IP, and Freeze Bridge IP. You'll also see how to use these IP to implement either an internal or external host design.
Partial Reconfiguration for Intel FPGA Devices: Output Files & Demonstration	Partial Reconfiguration Training part 4 of 4. This final part of the training discusses the entire design flow for a PR project. It also looks at the files output from the flow. Also included is a demonstration of a complete and functional PR design using the Intel Arria 10 GX development kit.

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Table 6 - Additional Videos

Intel® FPGA Quick Videos

Video Title	Description
Implementing a Partial Reconfiguration Design within Qsys for Intel FPGAs	Watch this video to learn how to implement Partial Reconfiguration Design within Qsys for Intel FPGAs.
Remote System Upgrade and Update EPCQ Data Over System Console on Cyclone 10 LP FPGA	Watch this video to learn how to perform Remote System Upgrade feature on Intel Cyclone 10 LP FPGA
Arria 10 Configuration via Protocol (CvP)	Watch this video to learn how to configure your Intel Arria 10 device using the PCIe protocol.
How to Customize JAM File for Multiple JTAG Devices in a Single JTAG Chain Part1	Watch this video to learn about customizing JAM files for a board with multi-device JTAG chains.
How to Customize JAM File for Multiple JTAG Devices in a Single JTAG Chain Part2	Watch this video to learn about customizing JAM files for a board with multi-device JTAG chains.
How to Perform Active Serial (AS) Configuration via JTAG Interface Using Serial Flash Loader IP Core	Watch this video to learn about configuration schemes other than the usual JTAG configuration. Additionally, this video covers the serial flash loader (SFL) IP core.

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Board Developer Center - Contains detailed guidelines and considerations for high-speed PCB designs with Intel® FPGAs and SoC FPGAs.
Embedded Software Developer Center - Contains guidance on how to design in an embedded environment with SoC FPGAs.
FPGA Developer Center - Contains resources to complete your Intel® FPGA design.

1. Device Specific Configuration Details
2. Configuration Schemes and IP
3. Advanced Configuration Features
4. Intel® Quartus® Prime Software Design Flow
5. Board Design
6. Debug
Design Examples and Reference Designs

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Device Configuration - Support Center

1. Device Specific Configuration Details

Table 1 - Configuration Schemes and Features Overview

2. Configuration Schemes and IP

3. Advanced Configuration Features

4. Intel® Quartus® Prime Software Design Flow

Table 2 - Device Configuration Setting and Programming Files Generation Flow

5. Board Design

6. Debug

Configuration Devices

Table 3 - Intel® FPGA Configuration Devices

Table 4 - Intel Supported Third Party Configuration Devices

Design Examples and Reference Designs

Table 5 - Training Courses and Videos

Table 6 - Additional Videos

Still Have Questions?

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