Device Configuration - Support Center

Table 1 - Configuration Schemes and Features Overview

Device Family Configuration Schemes Configuration Features
 

Scheme

Data Width

Max Clock Rate

Max Data Rate

Design Security

Partial Reconfiguration (2)

Remote System Update

Single Event Upsets

Configuration via Protocol

Intel Agilex

Avalon® Streaming

32 bits

125 MHz

4000 Mbps

Parallel Flash Loader II IP core

N/A

16 bits

125 MHz

2000 Mbps

8 bits

125 MHz

1000 Mbps

Active Serial (AS)

4 bits

166(1) MHz

664 Mbps

JTAG

1 bit

30 MHz

30 Mbps

N/A

N/A

Intel® Stratix® 10

Avalon®-ST

32 bits

125 MHz

4000 Mbps

Parallel Flash Loader II IP core

N/A

16 bits

125 MHz

2000 Mbps

8 bits

125 MHz

1000 Mbps

Active Serial (AS)

4 bits

125(1) MHz

500 Mbps

JTAG

1 bit

30 MHz

30 Mbps

N/A

N/A

Intel® Arria® 10

Configuration via HPS

32 bits

100 MHz

3200 Mbps

via HPS

N/A

16 bits

100 MHz

1600 Mbps

Fast Passive Parallel (FPP)

32 bits

100 MHz

3200 Mbps

Parallel Flash Loader IP core

N/A

16 bits

100 MHz

1600 Mbps

8 bits

100 MHz 

800 Mbps

Active Serial (AS)

4 bits

100 MHz

400 Mbps

(3)

1 bit

100 MHz

100 Mbps

Passive Serial (PS)

1 bit

100 MHz

100 Mbps

(3)

Parallel Flash Loader IP core

N/A

JTAG

1 bit

33 MHz

33 Mbps

 

(3)

N/A

N/A

Intel® Cyclone® 10 GX

Fast Passive Parallel (FPP)

32 bits

100 MHz

3200 Mbps

Parallel Flash Loader IP core

N/A

16 bits

100 MHz

1600 Mbps

8 bits

100 MHz 

800 Mbps

Active Serial (AS)

4 bit

100 MHz

400 Mbps

(3)

1 bits

100 MHz

100 Mbps

Passive Serial (PS)

1 bit

100 MHz

100 Mbps

(3)

Parallel Flash Loader IP core

N/A

JTAG

1 bit

33 MHz

33 Mbps

N/A

(3)

N/A

N/A

Intel® Cyclone® 10 LP

Fast Passive Parallel (FPP)

8 bits

66(4)/100(6) MHz

528(4)/800(6) Mbps

N/A

N/A

Parallel Flash Loader IP core

N/A

Passive Serial (PS)

1 bit

66(4)/133(5) MHz

66(4)/133(5) Mbps

N/A

N/A

Parallel Flash Loader IP core

N/A

Active Serial (AS)

1 bit

40 MHz

40 Mbps

N/A

N/A

N/A

JTAG

1 bit

25 MHz

25 Mbps

N/A

N/A

N/A

N/A

Table 2 - Device Configuration Setting and Programming Files Generation Flow

 

1. General Setting

  • General page of the Device and Pin Options dialog box in the Intel Quartus Prime Software.
  • Specify the device options. These options are independent on the configuration scheme.

2. Configuration Setting

  • Configuration page of the Device and Pin Options dialog box in the Intel Quartus Prime Software.
  • Specify the Device Configuration scheme, Configuration Device setting and Configuration Pin setting.

3. Programming Files Setting

  • Programming Files page of the Device and Pin Options dialog box in the Intel Quartus Prime Software.
  • Select the programming file format to generate. Selecting the programming file in this page is optional, user is recommended to use the Convert Programming File or Programming File Generator to convert/generate the type of programming file for the used of selected configuration scheme.

4. Others Optional Advanced Feature Setting

  • Error Detection CRC, CvP Settings and Partial Reconfiguration page of the Device and Pin Options dialog box in the Intel Quartus Prime Software.
  • Error Detection CRC page - Specify whether error detection is used and the rate at which it is checked.
  • CvP Settings page - Specify the type of CvP settings.
  • Partial Reconfiguration page - Specify Partial Reconfiguration settings.

5. Generate Configuration and Programming Files

  • Once design compilation is completed, the Convert Programming Files or Programming File Generator is the tool in Intel Quartus Prime Software to convert/generate the type of programming file for selected configuration scheme or configuration feature.

Table 3 - Intel Supported Third Party Configuration Devices

Intel FPGA

Vendor

P/N

Byte addressing

Dummy Clock Settings

ASx1 ASx4

Permanent Quad-Enabled flash?

Intel Tested and Supported Flash Devices

Intel Agilex

Micron

MT25QU128

3-byte(1)

N/A

10(4)

No(6)

MT25QU128ABA8ESF-0SIT

MT25QU256

MT25QU256ABA8E12-1SIT

MT25QU512

MT25QU512ABB8ESF-0SIT

MT25QU01G

MT25QU01GBBB8ESF-0SIT

MT25QU02G

MT25QU02GCBB8E12-0SIT

Macronix

MX25U128(10)

3-byte(1)

N/A

6(1)

No(6)

MX25U12835FMI-100

MX25U256(10)

MX25U25645GMI00

MX25U512(10)

MX25U51245GMI00

MX66U512(10)

MX66U51235FXDI-10G

MX66U1G(10)

MX66U1G45GXDI00

MX66U2G(10)

MX66U2G45GXRI00

ISSI

IS25WP512M

3-byte(1)

N/A

6(1)

No(6)

IS25WP512M-RHLE

Intel Stratix 10

Micron

MT25QU128

3-byte(1)

N/A

10(4)

No(6)

MT25QU128ABA8ESF-0SIT

MT25QU256

MT25QU256ABA8E12-1SIT

MT25QU512

MT25QU512ABB8ESF-0SIT

MT25QU01G

MT25QU01GBBB8ESF-0SIT

MT25QU02G

MT25QU02GCBB8E12-0SIT

Macronix

MX25U128(10)

3-byte(1)

N/A

6(1)

No(6)

MX25U12835FMI-100

MX25U256(10)

MX25U25645GMI00

MX25U512(10)

MX25U51245GMI00

MX66U512(10)

MX66U51235FXDI-10G

MX66U1G(10)

MX66U1G45GXDI00

MX66U2G(10)

MX66U2G45GXRI00

Intel Arria 10, Intel Cyclone 10 GX

Micron

MT25QU256

4-byte(4)

10(4)

10(4)

No(6)

MT25QU256ABA8E12-1SIT

MT25QU512

MT25QU512ABB8ESF-0SIT

MT25QU01G

MT25QU01GBBB8ESF-0SIT

MT25QU02G

MT25QU02GCBB8E12-0SIT

Macronix

MX25U256(3)

4-byte(5)

10(5)

10(5)

Yes(6)

MX25U25645GXDI54

MX25U512(3)

MX25U51245GXDI54

MX66U1G(3)

MX66U1G45GXDI54

MX66U2G(3)

MX66U2G45GXRI54

Cyclone V, Arria V, Stratix V

Micron

MT25QL128

3-byte(1)

12(4)

12(4)

No(6)

MT25QL128ABA8ESF-0SIT

MT25QL256

4-byte(4)

4(4)

10(4)

No(6)

MT25QL256ABA8ESF-0SIT

MT25QL512

MT25QL512ABB8ESF-0SIT

MT25QL01G

MT25QL01GBBB8ESF-0SIT

MT25QL02G

MT25QL02GCBB8E12-0SIT

Macronix

MX25L128

3-byte(1)(2)

8(1)

6(1)

No(6)

MX25L12833FMI-10G

MX25L256

MX25L25645GMI-08G

MX25L512

MX25L51245GMI-08G

Cypress

S25FL128

3-byte(1)(2)

8(1)

7(1)

No(6)

S25FL128SAGMFI000

S25FL256

S25FL256SAGMFI000

S25FL512

S25FL512SAGMFI0I0

Cyclone 10 LP

Micron

MT25QL128

3-byte(1)(2)

8(1)

N/A

No(6)

MT25QL128ABA8ESF-0SIT

MT25QL256

MT25QL256ABA8ESF-0SIT

MT25QL512

MT25QL512ABB8ESF-0SIT

MT25QL01G

MT25QL01GBBB8ESF-0SIT

MT25QL02G

MT25QL02GCBB8E12-0SIT

Macronix

MX25L128

3-byte(1)(2)

8(1)

N/A

No(6)

MX25L12833FMI-10G

MX25L256

MX25L25645GMI-08G

MX25L512

MX25L51245GMI-08G

Cypress

S25FL128

3-byte(1)(2)

8(1)

N/A

No(6)

S25FL128SAGMFI000

S25FL256

S25FL256SAGMFI000

S25FL512

S25FL512SAGMFI0I0

Title

Type

Description

Introduction to Configuring Intel FPGAs

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Learn the configuration schemes, solutions, features and tools available for configuring Intel FPGAs and programming configuration devices.

Configuration Schemes for Intel FPGAs

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Learn the difference between all the configuration schemes that can be used to configure Intel FPGAs.

Configuration Solutions for Intel FPGAs

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Learn about the Intel FPGAs configuration devices, serial and parallel flash loaders and the embedded configuration solutions

Configuration for Intel Stratix 10 Devices

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Learn the unique configuration features available in the Intel Stratix 10 devices

Remote System Upgrade in Intel MAX 10 Devices

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Learn how to set up and perform a RSU in an Intel MAX 10 device

Creating Second Stage Bootloader for Intel FPGA SoCs

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Learn the flow and tools available to quickly customize and generate the second stage boot software

Secure Boot with Intel Arria 10 SoC FPGAs

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Learn to generate and program Intel® Arria® 10 SoC FPGAs with and encrypted and/or signed second stage boot image

Mitigating Single Event Upsets in Intel Arria 10 and Intel Cyclone 10 GX Devices

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Learn the features of the Intel® Arria® 10 and Intel Cyclone 10 GX device families that can be used in the designing your own SEU mitigation solution

SEU Mitigation in Intel FPGA Devices: Hierarchy Tagging

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Learn how you can improve your sensitivity processing solution by supplementing single event upset (SEU) mitigation technique with feature called hierarchy tagging

SEU Mitigation in Intel FPGA Devices: Fault Injection

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Learn about Fault Injection IP core and Fault Injection Debugger software to reduce Failure in Time (FIT) rate

Using the Generic Serial Flash Interface

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Learn how to use the Generic Serial Flash Interface Intel FPGA IP Core to program any serial peripheral interface (SPI) type flash device

SoC Hardware Overview: Flash Controllers and Interface Protocols

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Learn about the Hard Processor Subsystem (HPS) found on the Cyclone V, Arria V, and Arria 10 SoCs. The online training includes information about the non-volatile storage controllers and the various interface protocols.

Partial Reconfiguration for Intel FPGA Devices: Introduction & Project Assignments

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Partial Reconfiguration Training part 1 of 4. This part of the training introduces you to the PR feature and the general design flow for a PR design. You'll also learn about design partition and Logic Lock region assignments, required assignments for implementing a PR design, and recommendations for how to floorplan a design for PR.

Partial Reconfiguration for Intel FPGA Devices: Design Guidelines & Host Requirements

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Partial Reconfiguration Training part 2 of 4. This part of the training discusses the guidelines for creating a PR design, including the creation of a port superset and freeze logic. It also discusses the requirements for a PR host, the logic added to the design's static region or an external device to control PR operations.

Partial Reconfiguration for Intel FPGA Devices: PR Host IP & Implementations

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 Partial Reconfiguration Training part 3 of 4. This part of the training discusses all of the PR IP included in the Intel Quartus Prime software, including the PR Controller IP, Region Controller IP, and Freeze Bridge IP. You'll also see how to use these IP to implement either an internal or external host design.

Partial Reconfiguration for Intel FPGA Devices: Output Files & Demonstration

Online

Partial Reconfiguration Training part 4 of 4. This final part of the training discusses the entire design flow for a PR project. It also looks at the files output from the flow. Also included is a demonstration of a complete and functional PR design using the Intel Arria 10 GX development kit.

Title 

Description

Implementing a Partial Reconfiguration Design within Qsys for Intel FPGAs

Watch this video to learn how to implement Partial Reconfiguration Design within Qsys for Intel FPGAs.

Remote System Upgrade and Update EPCQ Data Over System Console on Cyclone 10 LP FPGA

Watch this video to learn how to perform Remote System Upgrade feature on Intel Cyclone 10 LP FPGA

Arria 10 Configuration via Protocol (CvP)

Watch this video to learn how to configure your Intel Arria 10 device using the PCIe protocol.

How to Customize JAM File for Multiple JTAG Devices in a Single JTAG Chain Part1

Watch this video to learn about customizing JAM files for a board with multi-device JTAG chains.

How to Customize JAM File for Multiple JTAG Devices in a Single JTAG Chain Part2

Watch this video to learn about customizing JAM files for a board with multi-device JTAG chains.

How to Perform Active Serial (AS) Configuration via JTAG Interface Using Serial Flash Loader IP Core

Watch this video to learn about configuration schemes other than the usual JTAG configuration. Additionally, this video covers the serial flash loader (SFL) IP core.