Device Configuration - Support Center
Welcome to the Device Configuration Support Center!
Here you will find information on how to select, design, and implement configuration schemes and features. There are also guidelines on how to bring up your system and debug the configuration links. This page is organized into categories that align with a configuration system design flow from start to finish.
Enjoy your journey!
Get support resources for Intel® Agilex™, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 devices from the pages below. For other devices, search from the following links: Documentation, Training Courses, Intel® FPGA Quick Videos, Intel® FPGA Design Examples, and FPGA Knowledge Base.
1. Device Specific Configuration Details
Table 1 - Configuration Schemes and Features Overview
| Device Family | Configuration Schemes | Configuration Features | |||||||
|---|---|---|---|---|---|---|---|---|---|
Scheme |
Data Width |
Max Clock Rate |
Max Data Rate |
Design Security |
Partial Reconfiguration (2) |
Remote System Update |
Single Event Upsets |
Configuration via Protocol |
|
Intel Agilex |
Avalon® Streaming |
32 bits |
125 MHz |
4000 Mbps |
√ |
√ |
Parallel Flash Loader II IP core |
√ |
N/A |
16 bits |
125 MHz |
2000 Mbps |
√ |
√ |
|||||
8 bits |
125 MHz |
1000 Mbps |
√ |
√ |
|||||
Active Serial (AS) |
4 bits |
166(1) MHz |
664 Mbps |
√ |
√ |
√ |
√ |
√ |
|
JTAG |
1 bit |
30 MHz |
30 Mbps |
√ |
√ |
N/A |
√ |
N/A |
|
Intel® Stratix® 10 |
Avalon®-ST |
32 bits |
125 MHz |
4000 Mbps |
√ |
√ |
Parallel Flash Loader II IP core |
√ |
N/A |
16 bits |
125 MHz |
2000 Mbps |
√ |
√ |
|||||
8 bits |
125 MHz |
1000 Mbps |
√ |
√ |
|||||
Active Serial (AS) |
4 bits |
125(1) MHz |
500 Mbps |
√ |
√ |
√ |
√ |
√ |
|
JTAG |
1 bit |
30 MHz |
30 Mbps |
√ |
√ |
N/A |
√ |
N/A |
|
Intel® Arria® 10 |
Configuration via HPS |
32 bits |
100 MHz |
3200 Mbps |
√ |
√ |
via HPS |
√ |
N/A |
16 bits |
100 MHz |
1600 Mbps |
√ |
||||||
Fast Passive Parallel (FPP) |
32 bits |
100 MHz |
3200 Mbps |
√ |
√ |
Parallel Flash Loader IP core |
√ |
N/A |
|
16 bits |
100 MHz |
1600 Mbps |
√ |
||||||
8 bits |
100 MHz |
800 Mbps |
√ |
||||||
Active Serial (AS) |
4 bits |
100 MHz |
400 Mbps |
√ |
√(3) |
√ |
√ |
√ |
|
1 bit |
100 MHz |
100 Mbps |
√ |
||||||
Passive Serial (PS) |
1 bit |
100 MHz |
100 Mbps |
√ |
√(3) |
Parallel Flash Loader IP core |
√ |
N/A |
|
JTAG |
1 bit |
33 MHz |
33 Mbps |
|
√(3) |
N/A |
√ |
N/A |
|
Intel® Cyclone® 10 GX |
Fast Passive Parallel (FPP) |
32 bits |
100 MHz |
3200 Mbps |
√ |
√ |
Parallel Flash Loader IP core |
√ |
N/A |
16 bits |
100 MHz |
1600 Mbps |
√ |
||||||
8 bits |
100 MHz |
800 Mbps |
√ |
||||||
Active Serial (AS) |
4 bit |
100 MHz |
400 Mbps |
√ |
√(3) |
√ |
√ |
√ |
|
1 bits |
100 MHz |
100 Mbps |
√ |
||||||
Passive Serial (PS) |
1 bit |
100 MHz |
100 Mbps |
√ |
√(3) |
Parallel Flash Loader IP core |
√ |
N/A |
|
JTAG |
1 bit |
33 MHz |
33 Mbps |
N/A |
√(3) |
N/A |
√ |
N/A |
|
Intel® Cyclone® 10 LP |
Fast Passive Parallel (FPP) |
8 bits |
66(4)/100(6) MHz |
528(4)/800(6) Mbps |
N/A |
N/A |
Parallel Flash Loader IP core |
√ |
N/A |
Passive Serial (PS) |
1 bit |
66(4)/133(5) MHz |
66(4)/133(5) Mbps |
N/A |
N/A |
Parallel Flash Loader IP core |
√ |
N/A |
|
Active Serial (AS) |
1 bit |
40 MHz |
40 Mbps |
N/A |
N/A |
√ |
√ |
N/A |
|
JTAG |
1 bit |
25 MHz |
25 Mbps |
N/A |
N/A |
N/A |
√ |
N/A |
|
- The maximum clock rate when using OSC_CLK_1 as configuration clock source. The maximum clock rate reduces if you use the internal oscillator as the configuration clock source, during SmartVID operation, or when the device is in user mode.
- You can perform partial reconfiguration after the device is fully configured. For more information, refer to the Partial Reconfiguration User Guide.
- Partial configuration can be performed only when it is configured as internal host.
- Supply voltage for internal logic, VCCINT = 1.0 V.
- Supply voltage for internal logic, VCCINT = 1.2 V.
- Supply voltage for internal logic, VCCINT = 1.2 V. Cyclone 10 LP 1.2 V core voltage devices support 133 MHz DCLK fMAX for 10CL006, 10CL010, 10CL016, 10CL025, and 10CL040 only.
2. Configuration Schemes and IP
Configuration User Guides
Intel Agilex Devices
Intel Stratix 10 Devices
Configuration via HPS
Configure the FPGA portion of the SoC device by utilizing Hard Processor System (HPS)
Intel Agilex Devices
Intel Stratix 10 Devices
- Intel Stratix 10 SoC FPGA Boot User Guide
- Intel Stratix 10 Hard Processor System Technical Reference Manual
Intel Arria 10 Devices
Fast Passive Parallel
Intel Arria 10 Devices
Intel Cyclone 10 GX Devices
Intel Cyclone 10 LP Devices
Additional Resources:
Active Serial
Intel Agilex Devices
Intel Stratix 10 Devices
Intel Arria 10 Devices
Intel Cyclone 10 GX Devices
Intel Cyclone 10 LP Devices
Additional Resources:
AN 370: Using the Intel FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software
AN 418: SRunner: An Embedded Solution for Serial Configuration Device Programming
Passive Serial
Intel Arria 10 GX Devices
Intel Cyclone 10 GX Devices
Intel Cyclone 10 LP Devices
Additional Resources:
JTAG
Intel Agilex Devices
Intel Stratix 10 Devices
Intel Arria 10 Devices
Intel Cyclone 10 GX Devices
Intel Cyclone 10 LP Devices
Additional Resources:
3. Advanced Configuration Features
Device Security
Intel Agilex Devices
Intel Stratix 10 Devices
Intel Arria 10 Devices
Intel Cyclone 10 GX Devices
Additional Resources:
Partial Reconfiguration
Partial Reconfiguration Support Page
Intel Agilex Devices
Intel Stratix 10 Devices
- Partial Reconfiguration Solutions IP User Guide
- AN 825: Partially Reconfiguring a Design on Intel Stratix 10 GX FPGA Development Board
- AN 826: Hierarchical Partial Reconfiguration Tutorial for Stratix 10 GX FPGA Development Board
- AN 818: Static Update Partial Reconfiguration Tutorial for Stratix 10 GX FPGA Development Board
- AN 819: Partial Reconfiguration over PCI Express* Reference Design for Intel Stratix 10 Devices
- AN 820: Hierarchical Partial Reconfiguration over PCI Express Reference Design for Intel Stratix 10 Devices
Intel® Arria® 10 Devices
- Partial Reconfiguration Solutions IP User Guide
- Arria® 10 CvP Initialization and Partial Reconfiguration via Protocol User Guide
- AN 817: Static Update Partial Reconfiguration Tutorial for Arria 10 GX FPGA Development Board
- AN 798: Partial Reconfiguration with the Arria 10 HPS
- AN 797: Partially Reconfiguring a Design on Intel Arria 10 GX FPGA Development Board
- AN 784: Partial Reconfiguration over PCI Express Reference Design for Intel Arria 10 Devices
- AN 805: Hierarchical Partial Reconfiguration of a Design on Intel Arria 10 SoC Development Board
- AN 806: Hierarchical Partial Reconfiguration Tutorial for Intel Arria 10 GX FPGA Development Board
- AN 813: Hierarchical Partial Reconfiguration over PCI Express Reference Design for Arria 10 Devices
Intel® Cyclone®10 GX Devices
Additional Resources:
Remote System Upgrade
Intel Agilex Devices
Intel Stratix 10 Devices
- Intel Stratix 10 Configuration User Guide
- Example of Tcl script used for the example for performing remote system update documented in the Remote System Upgrade section
- Intel Stratix 10 SoC Remote System Update (RSU) User Guide
Intel Arria 10 Devices
Intel Cyclone 10 GX Devices
Intel Cyclone 10 LP Devices
Additional Resources:
Single Event Upset (SEU) Mitigation
Intel Agilex Devices
Intel Stratix 10 Devices
Intel Arria 10 Devices
- Intel Arria 10 Core Fabric and General Purpose I/Os Handbook
- AN 737: SEU Detection and Recovery in Intel Arria 10 Devices
- Mitigating Single Event Upsets in Arria 10 Devices (Video)
Intel Cyclone 10 GX Devices
Intel Cyclone 10 LP Devices
Additional Resources:
Configuration via Protocol (CvP)
Configuration via Protocol Support Page
Intel Agilex Devices
Intel Stratix 10 Devices
Intel Arria 10 Devices
- Arria 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide
- Software driver code
Intel Cyclone 10 GX Devices
Flash Access IP
Intel Agilex Devices
- Mailbox Client Intel FPGA IP User Guide
- Mailbox Avalon ST Client Intel FPGA IP User Guide
- AN 932: Flash Access Migration Guidelines from Control Block-Based Devices to SDM-Based Devices
Intel Stratix 10 Devices
- Mailbox Client Intel FPGA IP User Guide
- Serial Flash Mailbox Client Intel FPGA IP User Guide
- AN 932: Flash Access Migration Guidelines from Control Block-Based Devices to SDM-Based Devices
Intel Arria 10 Devices
- Generic Serial Flash Interface Intel FPGA IP Core User Guide
- Active Serial Memory Interface (ASMI) Parallel Intel FPGA IP Core User Guide
- Active Serial Memory Interface (ASMI) Parallel II Intel FPGA IP Core User Guide
- AN 720: Simulating the ASMI Block in Your Design
Intel Cyclone 10 GX Devices
- Generic Serial Flash Interface Intel FPGA IP Core User Guide
- Active Serial Memory Interface (ASMI) Parallel I Intel® FPGA IP Core User Guide
- Active Serial Memory Interface (ASMI) Parallel II Intel FPGA IP Core User Guide
- AN 720: Simulating the Active Serial Memory Interface (ASMI) Block in Your Design
Intel Cyclone 10 LP Devices
Chip ID IP
Intel Agilex Devices
Intel Stratix 10 Devices
Intel Arria 10 Devices
Intel Cyclone 10 GX Devices
4. Intel® Quartus® Prime Software Design Flow
Table 2 - Device Configuration Setting and Programming Files Generation Flow
1. General Setting |
|
2. Configuration Setting |
|
3. Programming Files Setting |
|
4. Others Optional Advanced Feature Setting |
|
5. Generate Configuration and Programming Files |
|
Where Can I Find Information on Device Configuration Settings and Configuration & Programming Files Generation?
Intel Agilex Devices
Intel Stratix 10 Devices
Intel Arria 10 Devices
Intel Cyclone 10 GX Devices
Intel Cyclone 10 LP Devices
5. Board Design
Where Can I Find Information on Device Configuration Design Guidelines?
Intel Agilex Devices
Intel Stratix 10 Devices
Intel Arria 10 Devices
Intel Cyclone 10 GX Devices
Intel Cyclone 10 LP Devices
Where Can I Find Information on the Connection Guidelines for Configuration Pin?
Intel Agilex Devices
- Intel Agilex Device Family Pin Connection Guidelines - You can search using the keywords "Dedicated Configuration/JTAG Pins", "Secure Device Manager (SDM) Pins" and "Optional/Dual-Purpose Configuration Pins"
Intel Stratix 10 Devices
- Intel Stratix 10 GX, MX, TX and SX Device Family Pin Connection Guidelines - You can search using the keywords "Dedicated Configuration/JTAG Pins", "Secure Device Manager (SDM) Pins" and "Optional/Dual-Purpose Configuration Pins"
Intel Arria 10 Devices
- Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines - You can search using the keywords "Dedicated Configuration/JTAG Pins", "Optional/Dual-Purpose Configuration Pins" and "Partial Reconfiguration Pins"
Intel Cyclone 10 GX Devices
- Intel Cyclone 10 GX Device Family Pin Connection Guidelines - You can search using the keywords "Dedicated Configuration/JTAG Pins" and "Optional/Dual-Purpose Configuration Pins"
Intel Cyclone 10 LP Devices
- Intel Cyclone 10 LP Device Family Pin Connection Guidelines - You can search using the keywords "Configuration/JTAG Pins"
Where Can I Find Information on Configuration Specifications?
The configuration specification in the device datasheet specifies the following specifications:
- Timing specifications for configuration control pins
- Timing/Performance specifications for each of the supported configuration scheme
- Configuration bit stream sizes
- Configuration time estimation for each of the supported configuration scheme
Intel Agilex Devices
- Intel Agilex Device Datasheet - You can search using the keyword "Configuration Specifications" and "Power supply ramp time"
Intel Stratix 10 Devices
- Intel Stratix 10 Device Datasheet - You can search using the keyword "Configuration Specifications" and "Power supply ramp time"
Intel Arria 10 Devices
- Intel Arria 10 Device Datasheet - You can search using the keyword "Configuration Specifications" and "Power supply ramp time"
- Intel Arria 10 Core Fabric and General Purpose I/Os Handbook - You can search using the keywords "fast POR"
Intel Cyclone 10 GX Devices
- Intel Cyclone 10 GX Device Datasheet - You can search using the keyword "Configuration Specifications" and "Power supply ramp time"
- Intel Cyclone 10 GX Core Fabric and General Purpose I/Os Handbook - You can search using the keywords "fast POR"
Intel Cyclone 10 LP Devices
- Intel Cyclone 10 LP Device Datasheet - You can search using the keyword "Configuration and JTAG Specifications" and "Power supply ramp time"
- Intel Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook - You can search using the keywords "fast POR"
6. Debug
FPGA Configuration Troubleshooter
Intel Agilex and Intel Stratix 10 FPGA System Console Debugging Tool Using JTAG
Intel Stratix 10 FPGA SDM Debug Toolkit helps you debug your configuration issues.
- It is available in Intel Quartus Prime Pro Edition software v18.1 and onwards.
Searching a tool to debug configuration failures / design security / error detection cyclic redundancy check (CRC) on Intel® Arria® 10 devices?
- To get this configuration diagnostic tool, please contact your Intel® sales representative.
You can use this troubleshooter or fault tree analysis to identify possible configuration failure causes.
Knowledge Base Solution
Go to Knowledge Base, enter the keywords of the issue you face to find for the solution.
Intel® Supported Configuration Devices
Intel Supported Third Party Configuration Devices
Table 3 shows the criteria of third party configuration devices supported by Intel Quartus Convert Programming File Tools and Quartus Programmer version 21.3 Pro Edition and 20.1 Standard Edition.
Table 3 - Intel Supported Third Party Configuration Devices
Intel FPGA |
Vendor |
P/N |
Byte addressing |
Dummy Clock Settings ASx1 ASx4 |
Permanent Quad-Enabled flash? |
Intel Tested and Supported Flash Devices |
|
|---|---|---|---|---|---|---|---|
Intel Agilex |
Micron |
MT25QU128 |
3-byte(1) |
N/A |
10(4) |
No(6) |
MT25QU128ABA8ESF-0SIT |
MT25QU256 |
MT25QU256ABA8E12-1SIT |
||||||
MT25QU512 |
MT25QU512ABB8ESF-0SIT |
||||||
MT25QU01G |
MT25QU01GBBB8ESF-0SIT |
||||||
MT25QU02G |
MT25QU02GCBB8E12-0SIT |
||||||
Macronix |
MX25U128(10) |
3-byte(1) |
N/A |
6(1) |
No(6) |
MX25U12835FMI-100 |
|
MX25U256(10) |
MX25U25645GMI00 |
||||||
MX25U512(10) |
MX25U51245GMI00 |
||||||
MX66U512(10) |
MX66U51235FXDI-10G |
||||||
MX66U1G(10) |
MX66U1G45GXDI00 |
||||||
MX66U2G(10) |
MX66U2G45GXRI00 |
||||||
ISSI |
IS25WP512M |
3-byte(1) |
N/A |
6(1) |
No(6) |
IS25WP512M-RHLE |
|
Intel Stratix 10 |
Micron |
MT25QU128 |
3-byte(1) |
N/A |
10(4) |
No(6) |
MT25QU128ABA8ESF-0SIT |
MT25QU256 |
MT25QU256ABA8E12-1SIT |
||||||
MT25QU512 |
MT25QU512ABB8ESF-0SIT |
||||||
MT25QU01G |
MT25QU01GBBB8ESF-0SIT |
||||||
MT25QU02G |
MT25QU02GCBB8E12-0SIT |
||||||
Macronix |
MX25U128(10) |
3-byte(1) |
N/A |
6(1) |
No(6) |
MX25U12835FMI-100 |
|
MX25U256(10) |
MX25U25645GMI00 |
||||||
MX25U512(10) |
MX25U51245GMI00 |
||||||
MX66U512(10) |
MX66U51235FXDI-10G |
||||||
MX66U1G(10) |
MX66U1G45GXDI00 |
||||||
MX66U2G(10) |
MX66U2G45GXRI00 |
||||||
Intel Arria 10, Intel Cyclone 10 GX |
Micron |
MT25QU256 |
4-byte(4) |
10(4) |
10(4) |
No(6) |
MT25QU256ABA8E12-1SIT |
MT25QU512 |
MT25QU512ABB8ESF-0SIT |
||||||
MT25QU01G |
MT25QU01GBBB8ESF-0SIT |
||||||
MT25QU02G |
MT25QU02GCBB8E12-0SIT |
||||||
Macronix |
MX25U256(3) |
4-byte(5) |
10(5) |
10(5) |
Yes(6) |
MX25U25645GXDI54 |
|
MX25U512(3) |
MX25U51245GXDI54 |
||||||
MX66U1G(3) |
MX66U1G45GXDI54 |
||||||
MX66U2G(3) |
MX66U2G45GXRI54 |
||||||
Cyclone V, Arria V, Stratix V |
Micron |
MT25QL128 |
3-byte(1) |
12(4) |
12(4) |
No(6) |
MT25QL128ABA8ESF-0SIT |
MT25QL256 |
4-byte(4) |
4(4) |
10(4) |
No(6) |
MT25QL256ABA8ESF-0SIT |
||
MT25QL512 |
MT25QL512ABB8ESF-0SIT |
||||||
MT25QL01G |
MT25QL01GBBB8ESF-0SIT |
||||||
MT25QL02G |
MT25QL02GCBB8E12-0SIT |
||||||
Macronix |
MX25L128 |
3-byte(1)(2) |
8(1) |
6(1) |
No(6) |
MX25L12833FMI-10G |
|
MX25L256 |
MX25L25645GMI-08G |
||||||
MX25L512 |
MX25L51245GMI-08G |
||||||
Cypress |
S25FL128 |
3-byte(1)(2) |
8(1) |
7(1) |
No(6) |
S25FL128SAGMFI000 |
|
S25FL256 |
S25FL256SAGMFI000 |
||||||
S25FL512 |
S25FL512SAGMFI0I0 |
||||||
Cyclone 10 LP |
Micron |
MT25QL128 |
3-byte(1)(2) |
8(1) |
N/A |
No(6) |
MT25QL128ABA8ESF-0SIT |
MT25QL256 |
MT25QL256ABA8ESF-0SIT |
||||||
MT25QL512 |
MT25QL512ABB8ESF-0SIT |
||||||
MT25QL01G |
MT25QL01GBBB8ESF-0SIT |
||||||
MT25QL02G |
MT25QL02GCBB8E12-0SIT |
||||||
Macronix |
MX25L128 |
3-byte(1)(2) |
8(1) |
N/A |
No(6) |
MX25L12833FMI-10G |
|
MX25L256 |
MX25L25645GMI-08G |
||||||
MX25L512 |
MX25L51245GMI-08G |
||||||
Cypress |
S25FL128 |
3-byte(1)(2) |
8(1) |
N/A |
No(6) |
S25FL128SAGMFI000 |
|
S25FL256 |
S25FL256SAGMFI000 |
||||||
S25FL512 |
S25FL512SAGMFI0I0 |
||||||
- Using the default setting of the configuration devices.
- When performing remote system upgrade, the start address of the images must be set within first 128 Mb.
- Intel Arria 10 and Intel Cyclone 10 GX devices support only Macronix configuration devices with part number MX25U25645GXDI54, MX25U51245GXDI54, MX66U1G45GXDI54, MX66U2G45GXRI54.
- Intel Quartus Programmer set the non-volatile configuration register during programming operation. User need to set the register manually if using a third-party programmer.
- The configuration devices is permanent to this value, user do not have the options to change this setting.
- Intel Quartus Programmer issues command to enable quad mode
- These configuration devices are not supported by legacy ASMI Parallel I Intel FPGA IP core and ASMI Parallel II Intel FPGA IP core. For new design, please refer to Generic Serial Flash Interface Intel FPGA IP core.
- AS x 1 - Active serial configuration support 1 bit data width
- AS x 4 - Active serial configuration scheme support 4 bit data width
- Intel Stratix 10 and Intel Agilex device doesn't support Macronix configuration devices with part number MX25U25645GXDI54, MX25U51245GXDI54, MX66U1G45GXDI54 and MX66U2G45GXRI54.
Design Examples and Reference Designs
Design Examples and Reference Designs
Intel Agilex Devices
- Agilex Mailbox Client Intel FPGA IP Core Design Example (QSPI flash Access and Remote System Update)
- Chip ID Reading using AVST Mailbox IP in Agilex
- Intel Agilex P-tile CvP Example Design for Initialization mode
Intel Stratix 10 Devices
- Stratix 10 Mailbox Client Intel FPGA IP Core Design Example (QSPI flash Access and Remote System Update)
- Intel Stratix 10 CvP Initialization Design Example
- Intel Stratix 10 H-Tile CvP Design Example
- Intel Stratix 10 H-tile CvP Example Design for Initialization mode
- Intel Stratix 10 H-tile CvP Example Design for Update mode
- Stratix 10 Serial Flash Mailbox Client Intel FPGA IP Core Design Example
Intel Arria 10 Devices
- CvP Example Designs for Arria 10 GX FPGA Development Kit (FPGA Wiki)
- Intel Arria 10 Remote System Update (RSU) with Avalon-MM Interface (FPGA Wiki)
- Board Update Portal Utilizing EPCQ Flash Memory Reference Design
- Intel Arria 10 Configuration via PCIe Init Reference Design
- Remote System Update
- Customizable Flash Programmer for Arria 10
Intel Cyclone 10 GX Devices
Intel Cyclone 10 LP Devices
Training Courses and Videos
Training Courses
Title |
Type |
Description |
|---|---|---|
Online |
Learn the configuration schemes, solutions, features and tools available for configuring Intel FPGAs and programming configuration devices. |
|
Online |
Learn the difference between all the configuration schemes that can be used to configure Intel FPGAs. |
|
Online |
Learn about the Intel FPGAs configuration devices, serial and parallel flash loaders and the embedded configuration solutions |
|
Online |
Learn the unique configuration features available in the Intel Stratix 10 devices |
|
Online |
Learn how to set up and perform a RSU in an Intel MAX 10 device |
|
Online |
Learn the flow and tools available to quickly customize and generate the second stage boot software |
|
Online |
Learn to generate and program Intel® Arria® 10 SoC FPGAs with and encrypted and/or signed second stage boot image |
|
Mitigating Single Event Upsets in Intel Arria 10 and Intel Cyclone 10 GX Devices |
Online |
Learn the features of the Intel® Arria® 10 and Intel Cyclone 10 GX device families that can be used in the designing your own SEU mitigation solution |
Online |
Learn how you can improve your sensitivity processing solution by supplementing single event upset (SEU) mitigation technique with feature called hierarchy tagging |
|
Online |
Learn about Fault Injection IP core and Fault Injection Debugger software to reduce Failure in Time (FIT) rate |
|
Online |
Learn how to use the Generic Serial Flash Interface Intel FPGA IP Core to program any serial peripheral interface (SPI) type flash device |
|
SoC Hardware Overview: Flash Controllers and Interface Protocols |
Online |
Learn about the Hard Processor Subsystem (HPS) found on the Cyclone V, Arria V, and Arria 10 SoCs. The online training includes information about the non-volatile storage controllers and the various interface protocols. |
Partial Reconfiguration for Intel FPGA Devices: Introduction & Project Assignments |
Online |
Partial Reconfiguration Training part 1 of 4. This part of the training introduces you to the PR feature and the general design flow for a PR design. You'll also learn about design partition and Logic Lock region assignments, required assignments for implementing a PR design, and recommendations for how to floorplan a design for PR. |
Partial Reconfiguration for Intel FPGA Devices: Design Guidelines & Host Requirements |
Online |
Partial Reconfiguration Training part 2 of 4. This part of the training discusses the guidelines for creating a PR design, including the creation of a port superset and freeze logic. It also discusses the requirements for a PR host, the logic added to the design's static region or an external device to control PR operations. |
Partial Reconfiguration for Intel FPGA Devices: PR Host IP & Implementations |
Online |
Partial Reconfiguration Training part 3 of 4. This part of the training discusses all of the PR IP included in the Intel Quartus Prime software, including the PR Controller IP, Region Controller IP, and Freeze Bridge IP. You'll also see how to use these IP to implement either an internal or external host design. |
Partial Reconfiguration for Intel FPGA Devices: Output Files & Demonstration |
Online |
Partial Reconfiguration Training part 4 of 4. This final part of the training discusses the entire design flow for a PR project. It also looks at the files output from the flow. Also included is a demonstration of a complete and functional PR design using the Intel Arria 10 GX development kit. |
Title |
Description |
|---|---|
Implementing a Partial Reconfiguration Design within Qsys for Intel FPGAs |
Watch this video to learn how to implement Partial Reconfiguration Design within Qsys for Intel FPGAs. |
Remote System Upgrade and Update EPCQ Data Over System Console on Cyclone 10 LP FPGA |
Watch this video to learn how to perform Remote System Upgrade feature on Intel Cyclone 10 LP FPGA |
Watch this video to learn how to configure your Intel Arria 10 device using the PCIe protocol. |
|
How to Customize JAM File for Multiple JTAG Devices in a Single JTAG Chain Part1 |
Watch this video to learn about customizing JAM files for a board with multi-device JTAG chains. |
How to Customize JAM File for Multiple JTAG Devices in a Single JTAG Chain Part2 |
Watch this video to learn about customizing JAM files for a board with multi-device JTAG chains. |
How to Perform Active Serial (AS) Configuration via JTAG Interface Using Serial Flash Loader IP Core |
Watch this video to learn about configuration schemes other than the usual JTAG configuration. Additionally, this video covers the serial flash loader (SFL) IP core. |