Visible to Intel only — GUID: zwb1485172524059
Ixiasoft
Visible to Intel only — GUID: zwb1485172524059
Ixiasoft
6.1.4. JTAG Configuration
In Intel® Cyclone® 10 LP devices, JTAG instructions take precedence over other configuration schemes.
JTAG configuration can take place without waiting for other configuration modes to complete. For example, if you attempt JTAG configuration in Intel® Cyclone® 10 LP devices during PS configuration, PS configuration terminates and JTAG configuration begins. If the MSEL pins are set to AS mode, the Intel® Cyclone® 10 LP device does not transmit a DCLK signal when JTAG configuration takes place.
JTAG has developed a specification for boundary-scan testing (BST). The BST architecture offers the capability to efficiently test components on PCBs with tight lead spacing. The BST architecture can test pin connections without using physical test probes and capture functional data while a device is normally operating. You can also use the JTAG circuitry to shift configuration data into the device.
The Intel® Quartus® Prime software generates an .sof that you can use for JTAG configuration using a download cable in the Intel® Quartus® Prime software programmer.
Pin Name | Pin Type | Description |
---|---|---|
TDI | Test data input |
|
TDO | Test data output |
|
TMS | Test mode select |
|
TCK | Test clock input |
|
You can download data to the device through the Intel FPGA download cable or the Intel FPGA Ethernet cable during JTAG configuration. Configuring devices with a cable is similar to programming devices in-system.
Alternatively, you can use the JRunner software with .rbf or a JAM™ Standard Test and Programming Language (STAPL) Format File (.jam) or JAM Byte Code File (.jbc) with other third-party programmer tools.
Section Content
Configuring Intel Cyclone 10 LP Devices with the JRunner Software Driver
Configuring Intel Cyclone 10 LP Devices with Jam STAPL
JTAG Single-Device Configuration
JTAG Multi-Device Configuration
Combining JTAG and AS Configuration Schemes
Programming Serial Configuration Devices In-System with the JTAG Interface
JTAG Instructions
JTAG Configuration Connection Guidelines
Consider the following guidelines when you configure the Intel® Cyclone® 10 LP devices:
- Connect the pull-up resistors of the FPGA device to the VCC supply of the bank in which the pin resides.
- You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed the nCE pin of another device.
- The MSEL pin settings vary for different configuration voltage standards and POR time.
- The nCSO and ASDO pins are dual-purpose I/O pins. The ASDO pin also functions as the DATA[1] pin in FPP mode.
- For multi-device configurations, connect the pull-up resistor of the slave FPGA device(s) to the VCCIO supply voltage of I/O bank in which the nCE pin resides.
- Connect the repeater buffers between the master and slave devices of the FPGA device for DATA[0] and DCLK. All I/O inputs must maintain a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation.
- The 50 Ω series resistors are optional if the 3.3 V configuration voltage standard is applied. For optimal signal integrity, connect these 50 Ω series resistors if the 2.5 V or 3.0 V configuration voltage standard is applied.