Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

2.3.1.3. ROM: 1-PORT IP Core References

The ROM: 1-PORT IP core implements the single-port ROM memory mode.

Figure 21. ROM: 1-PORT IP Core Signals with the Single Clock Option Enabled


Figure 22. ROM: 1-PORT IP Core Signals with the Dual Clock: Use Separate 'Input' and 'Output' Clocks Option Enabled


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