Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

6.3.2.2. Reset

After power up, Intel® Cyclone® 10 LP devices go through POR.

POR delay is the time frame between the time when all the power supplies monitored by the POR circuitry reach the recommended operating voltage and when nSTATUS is released high and the Intel® Cyclone® 10 LP device is ready to begin configuration.

Set the POR delay using the MSEL pins. During POR, the device resets, holds nSTATUS and CONF_DONE low, and tri-states all user I/O pins (for PS and FPP configuration schemes only). To tri-state the configuration bus for AS configuration schemes, you must tie nCE high and nCONFIG low.

The user I/O pins and dual-purpose I/O pins have weak pull-up resistors, which are always enabled (after POR) before and during configuration.
  • When the device exits POR, all user I/O pins continue to tri-state. While nCONFIG is low, the device is in reset.
  • When nCONFIG goes high, the device exits reset and releases the open-drain nSTATUS pin, which is then pulled high by an external 10 kΩ pull-up resistor.
  • After nSTATUS is released, the device is ready to receive configuration data and the configuration stage starts.

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