Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

6.3.1. MSEL Pin Settings

To select a configuration scheme, hardwire the MSEL pins to VCCA or GND without pull-up or pull-down resistors.
Table 44.  MSEL Pin Settings for Each Configuration Scheme of Intel® Cyclone® 10 LP Devices with MSEL[3:0] Pins
Configuration Scheme Valid MSEL[3..0] POR Delay Configuration Voltage Standard (V)

AS

1101 Fast 3.3
0100 Fast 3.0
0010 Standard 3.3
0011 Standard 3.0

PS

1100 Fast 3.3/3.0/2.5
0000 Standard 3.3/3.0/2.5

FPP

1110 Fast 3.3/3.0/2.5
1111 Fast 1.8/1.5

Smaller Intel® Cyclone® 10 LP devices or package options (E144, M164, and U256) do not have the MSEL[3] pin. To configure these devices, select the MSEL[2:0] pins according to the table below.

Table 45.  MSEL Pin Settings for AS Configuration Scheme with MSEL[2:0] Pins
Configuration Scheme Valid MSEL[2..0] POR Delay Configuration Voltage Standard (V)

AS

101 Fast 3.3
010 Standard 3.3
011 Standard 3.0

PS

100 Fast 3.3/3.0/2.5
000 Standard 3.3/3.0/2.5

FPP

110 Fast 3.3/3.0/2.5
111 Fast 1.8/1.5
Note: The configuration voltage standard applies to the VCCIO supply of the bank in which the configuration pins reside.
For JTAG-based configuration schemes, the MSEL pin settings are ignored. Do not leave the MSEL pins floating. Connect them to Vcca or GND. These pins support the non-JTAG configuration scheme used in production. Intel recommends you connect the MSEL pins to GND if your device is only using JTAG configuration.
Note: You must also select the configuration scheme in the Configuration page of the Device and Pin Options dialog box in the Intel® Quartus® Prime software. Based on your selection, the option bit in the programming file is set accordingly.

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