Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

2.4. Intel® Cyclone® 10 LP Embedded Memory Clock Modes

Clock Mode Description Modes
True Dual-Port Simple Dual-Port Single-Port ROM FIFO
Independent Clock Mode

A separate clock is available for the following ports:

  • Port A—Clock A controls all registers on the port A side.
  • Port B—Clock B controls all registers on the port B side.
Yes Yes
Input/Output Clock Mode
  • M9K memory blocks can implement input or output clock mode for single-port, true dual-port, and simple dual-port memory modes.
  • An input clock controls all input registers to the memory block, including data, address, byteena, wren, and rden registers.
  • An output clock controls the data-output registers.
Yes Yes Yes Yes
Read or Write Clock Mode
  • M9K memory blocks support independent clock enables for both the read and write clocks.
  • A read clock controls the data outputs, read address, and read enable registers.
  • A write clock controls the data inputs, write address, and write enable registers.
Yes Yes
Single-Clock Mode

A single clock, together with a clock enable, controls all registers of the memory block.

Yes Yes Yes Yes Yes

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