Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Document Table of Contents Passive Serial Single-Device Configuration Using a Download Cable

To configure Intel® Cyclone® 10 LP device, connect the device to a download cable.

The download cable could be an Intel FPGA download cable or Intel FPGA Ethernet cable.
Note: Power up the VCC of the Intel FPGA download cable with a 2.5 V supply from VCCA. Third-party programmers must switch to 2.5 V.
Figure 91. Single Device PS Configuration Using an Intel Download Cable
Note: The pull-up resistors on DATA[0] and DCLK are only required if the download cable is the only configuration scheme used on your board. This is to ensure that DATA[0] and DCLK are not left floating after configuration. For example, if you also use a configuration device, the pull-up resistors on DATA[0] and DCLK are not required.

  1. The configuration begins when the external host transfers data from a storage device to the Intel® Cyclone® 10 LP through the download cable.
  2. The programming hardware or download cable then places the configuration data one bit at a time on the DATA[0] pin of the device.
  3. The configuration data clocks into the target device until CONF_DONE goes high.
    Note: The CONF_DONE pin must have an external 10-kΩ pull-up resistor for the device to initialize.

When you use the Intel FPGA download cable, setting the Auto-restart configuration after error option does not affect the configuration cycle because you must manually restart configuration in the Intel® Quartus® Prime software if an error occurs. The Enable user-supplied start-up clock (CLKUSR) option has no effect on device initialization, because this option is disabled in the .sof when programming the device with the Intel® Quartus® Prime Programmer and download cable. If you turn on the Enable user-supplied start-up clock (CLKUSR) option, you do not have to provide a clock on CLKUSR when you configure the device with the Intel® Quartus® Prime Programmer and a download cable.

You can also use the Intel FPGA download cable to configure multiple Intel® Cyclone® 10 LP device configuration pins. These pins are connected to every device in the chain:
  • DCLK
  • DATA[0]

All devices in the chain utilize and enter user mode at the same time because all the CONF_DONE pins are tied together. The entire chain halts configuration if any device detects an error because the nSTATUS pins are tied together.

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