Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Public
Document Table of Contents

4.2.13.1. PLL Reconfiguration Hardware

The following PLL components are configurable in real time:

  • Pre-scale counter (N)
  • Feedback counter (M)
  • Post-scale output counters (C0-C4)
  • Charge pump current (ICP)
  • Loop filter components (R, C)

You can dynamically adjust the charge pump current (ICP) and loop filter components (R, C) to facilitate on-the-fly reconfiguration of the PLL bandwidth.

Figure 56. PLL Reconfiguration Scan ChainThis figure shows the dynamic adjustment of the PLL counter settings by shifting their new settings into a serial shift register chain or scan chain. Serial data shifts to the scan chain via the scandata port, and shift registers are clocked by scanclk. The maximum scanclk frequency is 100 MHz. After shifting the last bit of data, asserting the configupdate signal for at least one scanclk clock cycle synchronously updates the PLL configuration bits with the data in the scan registers.

The counter settings are updated synchronously to the clock frequency of the individual counters. Therefore, not all counters update simultaneously.