Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

6.3.2.3. Configuration

Configuration data latches into the Intel® Cyclone® 10 LP at each DCLK cycle.

However, the width of the data bus and the configuration time taken differ for each scheme. After the device receives all the configuration data, the device releases the open-drain CONF_DONE pin, which is pulled high by an external 10 kΩ pull-up resistor.

A low-to-high transition on the CONF_DONE pin indicates that the configuration is complete and initialization of the device can begin.

Begin reconfiguration by pulling the nCONFIG pin low. The nCONFIG pin must be low for at least 500 ns. When nCONFIG is pulled low, the Intel® Cyclone® 10 LP device is reset.

The Intel® Cyclone® 10 LP device also pulls nSTATUS and CONF_DONE low and all I/O pins are tri-stated. Reconfiguration begins when nCONFIG returns to a logic-high level and the Intel® Cyclone® 10 LP device releases nSTATUS.

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