Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

7.3.1.4. Error Detection Frequency

You can control the speed of the error detection process by setting the division factor of the clock frequency in the Intel® Quartus® Prime software.

The divisor is , where n can be any value between 0 to 8.

The speed of the error detection process for each data frame is determined by this equation:

Table 55.  Error Detection Frequency Range for Intel® Cyclone® 10 LP Devices
Internal Oscillator Frequency Error Detection Frequency n Divisor Range
Maximum Minimum
80 MHz 80 MHz 312.5 kHz 0, 1, 2, 3, 4, 5, 6, 7, 8 1 – 256

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