Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

4.2.13.2. PLL Reconfiguration Implementation

To reconfigure the PLL counters, perform the following steps:

  1. Assert the scanclkena signal at least one scanclk cycle prior to shifting in the first bit of scandata (D0).
  2. Shift the serial data (scandata) into the scan chain on the second rising edge of scanclk.
  3. After all 144 bits have been scanned into the scan chain, deassert the scanclkena signal to prevent inadvertent shifting of bits in the scan chain.
  4. Assert the configupdate signal for one scanclk cycle to update the PLL counters with the contents of the scan chain.
    The scandone signal goes high indicating that the PLL is being reconfigured. A falling edge indicates that the PLL counters have been updated with new settings.
  5. Reset the PLL using the areset signal if you make any changes to the M, N, post-scale output C counters, or the ICP , R, and C settings.
  6. You can repeat steps 1 through 5 to reconfigure the PLL any number of times.
Figure 59. PLL Reconfiguration Scan Chain Functional Simulation

When reconfiguring the counter clock frequency, you cannot reconfigure the corresponding counter phase shift settings using the same interface. You can reconfigure phase shifts in real time using the dynamic phase shift reconfiguration interface. If you wish to keep the same nonzero phase shift setting (for example, 90°) on the clock output, you must reconfigure the phase shift after reconfiguring the counter clock frequency.

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