Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

9.4. Power-On Reset Circuitry

Intel® Cyclone® 10 LP devices contain POR circuitry to keep the device in a reset state until the power supply voltage levels have stabilized during power up. During POR, all user I/O pins are tri-stated until the power supplies reach the recommended operating levels. In addition, the POR circuitry also ensures the VCCIO level of I/O banks that contain configuration pins reach an acceptable level before configuration is triggered.

The POR circuit of the Intel® Cyclone® 10 LP device monitors the VCCINT, VCCA, and VCCIO (of banks 1, 5, 6, and 8) that contain configuration pins during power-on. You can power up or power down the VCCINT, VCCA, and VCCIO pins in any sequence. The VCCINT, VCCA, and VCCIO must have a monotonic rise to their steady state levels. All VCCA pins must be powered to 2.5V (even when phase-locked loops [PLLs] are not used), and must be powered up and powered down at the same time.

After the Intel® Cyclone® 10 LP device enters the user mode, the POR circuit continues to monitor the VCCINT and VCCA pins so that a brown-out condition during user mode is detected. If the VCCINT or VCCA voltage sags below the POR trip point during user mode, the POR circuit resets the device. If the VCCIO voltage sags during user mode, the POR circuit does not reset the device.

In some applications, it is necessary for a device to wake up very quickly to begin operation. Intel® Cyclone® 10 LP devices offer the Fast-On feature to support fast wake-up time applications. The MSEL pin settings determine the POR time (tPOR) of the device.

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