Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Document Table of Contents

6.1.3. Fast Passive Parallel Configuration

The FPP configuration scheme uses an external host, such as a microprocessor, MAX® II device, or MAX V device. This scheme allows for a faster configuration time.

You can use an external host to control the transfer of configuration data from an external storage such as flash memory to the FPGA. The design that controls the configuration process resides in the external host. You can store the configuration data in Raw Binary File (.rbf), Hexadecimal (Intel-Format) File (.hex), or Tabular Text File (.ttf) formats.

You can use the PFL IP core with a MAX II or MAX V device to read configuration data from the flash memory device and configure the Intel® Cyclone® 10 LP device.

  1. Two DCLK falling edges are required after the CONF_DONE pin goes high to begin the initialization of the device.
  2. The FPP configuration is not supported in E144 package of Intel® Cyclone® 10 LP devices.
  3. Intel® Cyclone® 10 LP devices do not support enhanced configuration devices for FPP configuration.

FPP Configuration Guidelines

Consider the following guidelines when you configure the Intel® Cyclone® 10 LP devices:

  • Connect the pull-up resistors of the FPGA device to the VCC supply of the bank in which the pin resides.
  • You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed the nCE pin of another device.
  • The MSEL pin settings vary for different configuration voltage standards and POR time.
  • The nCSO and ASDO pins are dual-purpose I/O pins. The ASDO pin also functions as the DATA[1] pin in FPP mode.
  • For multi-device configurations, connect the pull-up resistor of the slave FPGA device(s) to the VCCIO supply voltage of I/O bank in which the nCE pin resides.
  • Connect the repeater buffers between the master and slave devices of the FPGA device for DATA[0] and DCLK. All I/O inputs must maintain a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation.
  • The 50 Ω series resistors are optional if the 3.3 V configuration voltage standard is applied. For optimal signal integrity, connect these 50 Ω series resistors if the 2.5 V or 3.0 V configuration voltage standard is applied.