Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Document Table of Contents Bus LVDS I/O Standard in Intel® Cyclone® 10 LP Devices

The Bus LVDS I/O standard is a multipoint I/O standard that supports bidirectional half-duplex communication.

The Intel® Cyclone® 10 LP top, bottom, and right side I/O banks support the Bus LVDS I/O standard. For the Bus LVDS transmitter, Intel® Cyclone® 10 LP devices use emulated differential output. For the Bus LVDS receiver, Intel® Cyclone® 10 LP devices use the true LVDS input buffer. The transmitter and receiver share the same pins. Intel® Cyclone® 10 LP devices require an output enable (OE) signal to tristate the output buffers when the LVDS input buffer receives a signal.

The Bus LVDS bidirectional communication requires termination at both ends of the bus.
  • The termination resistor (RT) must match the bus differential impedance, which in turn depends on the loading on the bus. Increasing the load decreases the bus differential impedance.
  • With termination at both ends of the bus, termination is not required between the two signals at the input buffer.
  • Bus LVDS requires a single series resistor (RS) at the output buffer to match the impedance to the transmission line. The series resistor affects the voltage swing at the input buffer.
  • The maximum data rate achievable depends on many factors.
Figure 74. Typical Bus LVDS Topology with Multiple Intel® Cyclone® 10 LP Transmitters and Receivers
Note: Intel recommends that you perform simulation using the IBIS model while considering factors such as bus loading, termination values, and output and input buffer location on the bus to ensure that the required performance is achieved.