Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Document Table of Contents

7.2. User Mode Error Detection

In user mode, the contents of the configured configuration random-access memory (CRAM) bits may be affected by soft errors.

These soft errors, which are caused by an ionizing particle, are not common in Intel devices. However, high-reliability applications that require the device to operate error-free may require that your designs account for these errors.

You can enable the error detection circuitry to detect soft errors. This error detection circuitry continuously computes the CRC of the configured CRAM bits. The computed 32-bit CRC value is then compared with the 32-bit pre-calculated CRC value obtained at the end of the configuration. The process of error detection continues until the device is reset—by setting nCONFIG to low.

  • If the CRC values match, the resulting signature value is zero (CRC_ERROR= low) indicating the configured CRAM bits has no error.
  • Otherwise, the resulting signature value is non-zero (CRC_ERROR= high) to indicate a CRC error.

The Intel® Cyclone® 10 LP device error detection feature does not check memory blocks and I/O buffers. These device memory blocks support parity bits that are used to check the contents of memory blocks for any error. The I/O buffers are not verified during error detection because the configuration data uses flip-flops as storage elements that are more resistant to soft errors. Similar flip-flops are used to store the pre-calculated CRC and other error detection circuitry option bits.

Note: Intel® Cyclone® 10 LP devices also offer on-chip circuitry for automated SEU detection. For automated checking, you can implement the error detection CRC feature in the Intel® Quartus® Prime software with the existing circuitry in Intel® Cyclone® 10 LP devices.