Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Document Table of Contents

5.10. I/O and High Speed I/O in Intel® Cyclone® 10 LP Devices Revision History

Document Version Changes
2022.07.05 Updated the topic about the high-speed differential I/Os and SERDES to clarify that the devices use the DDIO registers in the IOE for the LVDS transmitters, and the DDIO registers in the core fabric for LVDS receivers.
2020.05.21 At the package plan table, added description and related information links that explain how the GPIO and LVDS pins are counted.
2019.01.15 Updated the table listing the programmable current strength to add missing information and to mark the default settings.
Date Version Changes
December 2017 2017.12.22
  • Updated the section about high-speed I/O timing budget:
    • Updated the high-speed I/O timing budget topic to clarify that Intel® Cyclone® 10 LP devices implements SERDES in LEs.
    • Removed information about obtaining RSKM report in the Intel® Quartus® Prime software. The software does not support generating RSKM report for Intel® Cyclone® 10 LP devices.
    • Removed the topic about assigning input delay to the LVDS receiver.
    • Added links to section about source-synchronous timing analysis and constraints in the LVDS SERDES Transmitter / Receiver IP Cores User Guide.
May 2017 2017.05.08 Initial release.