5.6.6. Programmable IOE Delay
Each pin can have a different delay value to ensure signals within a bus have the same delay going into or out of the device.
Each dual-purpose clock input pin provides a programmable delay to the global clock networks.
|Programmable Delays||Intel® Quartus® Prime Logic Option|
|Input pin-to-logic array delay||Input delay from pin to internal cells|
|Input pin-to-input register delay||Input delay from pin to input register|
|Output pin delay||Delay from output register to output pin|
|Dual-purpose clock input pin delay||Input delay from dual-purpose clock pin to fan-out destinations|
There are two paths in the IOE for an input to reach the logic array. Each of the two paths can have a different delay. This allows you to adjust delays from the pin to the internal logic element (LE) registers that reside in two different areas of the device. You must set the two combinational input delays with the input delay from pin to internal cells logic option in the Intel® Quartus® Prime software for each path. If the pin uses the input register, one of the delays is disregarded and the delay is set with the input delay from pin to input register logic option in the Intel® Quartus® Prime software.
The IOE registers in each I/O block share the same source for the preset or clear features. You can program preset or clear for each individual IOE, but you cannot use both features simultaneously. You can also program the registers to power-up high or low after configuration is complete. If programmed to power-up low, an asynchronous clear can control the registers. If programmed to power-up high, an asynchronous preset can control the registers. This feature prevents the inadvertent activation of the active-low input of another device upon power up. If one register in an IOE uses a preset or clear signal, all registers in the IOE must use that same signal if they require preset or clear. Additionally, a synchronous reset signal is available for the IOE registers.
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