Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

5.4. Intel® Cyclone® 10 LP I/O Elements

The Intel® Cyclone® 10 LP I/O elements (IOEs) contain a bidirectional I/O buffer and five registers for registering input, output, output-enable signals, and complete embedded bidirectional single data rate (SDR) and double data rate (DDR) transfer.

Note: Intel does not validate or support any IP that is intended for memory application, such as DDR, in Intel® Cyclone® 10 LP devices.

Each IOE contains one input register, two output registers, and two output-enable (OE) registers:

  • The two output registers and two OE registers are used for DDR applications.
  • You can use the input registers for fast setup times and output registers for fast clock-to-output times.
  • You can use the OE registers for fast clock-to-output enable times.

You can use the IOEs for input, output, or bidirectional data paths. The I/O pins support various single-ended and differential I/O standards.

Figure 62. IOE Structure in Bidirectional Configuration for SDR Mode


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