Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

4.1.2. GCLK Network Sources

Table 15.   Intel® Cyclone® 10 LP Clock Sources Connectivity to the GCLK Networks 10CL006 and 10CL010 devices only have GCLK networks 0 to 9.
GCLK Network Clock Sources GCLK Networks
CLK0/DIFFCLK_0p GCLK[0,2,4]
CLK1/DIFFCLK_0n GCLK[1,2]
CLK2/DIFFCLK_1p GCLK[1,3,4]
CLK3/DIFFCLK_1n GCLK[0,3]
CLK4/DIFFCLK_2p GCLK[5,7,9]
CLK5/DIFFCLK_2n GCLK[6,7]
CLK6/DIFFCLK_3p GCLK[6,8,9]
CLK7/DIFFCLK_3n GCLK[5,8]
CLK8/DIFFCLK_5n 4 GCLK[10,12,14]
CLK9/DIFFCLK_5p 4 GCLK[11,12]
CLK10/DIFFCLK_4n 4 GCLK[11,13,14]
CLK11/DIFFCLK_4p 4 GCLK[10,13]
CLK12/DIFFCLK_7n 4 GCLK[15,17,19]
CLK13/DIFFCLK_7p 4 GCLK[16,17]
CLK14/DIFFCLK_6n 4 GCLK[16,18,19]
CLK15/DIFFCLK_6p 4 GCLK[15,18]
PLL_1_C0 5 GCLK[0,3]
PLL_1_C1 5 GCLK[1,4]
PLL_1_C2 5 GCLK[0,2]
PLL_1_C3 5 GCLK[1,3]
PLL_1_C4 5 GCLK[2,4]
PLL_2_C0 5 GCLK[5,8]
PLL_2_C1 5 GCLK[6,9]
PLL_2_C2 5 GCLK[5,7]
PLL_2_C3 5 GCLK[6,8]
PLL_2_C4 5 GCLK[7,9]
PLL_3_C0 GCLK[10,13]
PLL_3_C1 GCLK[11,14]
PLL_3_C2 GCLK[10,12]
PLL_3_C3 GCLK[11,13]
PLL_3_C4 GCLK[12,14]
PLL_4_C0 GCLK[15,18]
PLL_4_C1 GCLK[16,19]
PLL_4_C2 GCLK[15,17]
PLL_4_C3 GCLK[16,18]
PLL_4_C4 GCLK[17,19]
DPCLK0 GCLK[0]
DPCLK1 GCLK[1]
DPCLK7 6, CDPCLK0, or CDPCLK7 4 7 GCLK[2]
DPCLK2 6, CDPCLK1, or CDPCLK2 4 7 GCLK[3,4]
DPCLK5 6, DPCLK7 4 GCLK[5]
DPCLK4 6, DPCLK6 4 GCLK[6]
DPCLK6 6, CDPCLK5, or CDPCLK6 4 7 GCLK[7]
DPCLK3 6, CDPCLK4, or CDPCLK3 4 7 GCLK[8,9]
DPCLK8 GCLK[10]
DPCLK11 GCLK[11]
DPCLK9 GCLK[12]
DPCLK10 GCLK[13,14]
DPCLK5 GCLK[15]
DPCLK2 GCLK[16]
DPCLK4 GCLK[17]
DPCLK3 GCLK[18,19]
4 These pins apply to all Intel® Cyclone® 10 LP devices except10CL006 and 10CL010 devices.
5 10CL006 and 10CL010 devices only have PLL_1 and PLL_2.
6 This pin applies only to 10CL006 and 10CL010 devices.
7 Only one of the two CDPCLK pins can feed the clock control block. You can use the other pin as a regular I/O pin.

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