Intel® Cyclone® 10 LP Device Family Pin Connection Guidelines

ID 683137
Date 11/09/2020
Public

Clock and PLL Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 1.  Clock and PLL Pins
Pin Name Pin Functions Pin Description Connection Guidelines
CLK[0,2,4,6,9,11,13,15], DIFFCLK_[0..7]p (Note 7) Clock, Input Dedicated global clock input pins that can also be used for the positive terminal inputs for differential global clock input or user input pins. Connect unused CLK or DIFFCLK pins to GND.
CLK[1,3,5,7,8,10,12,14], DIFFCLK_[0..7]n (Note 7) Clock, Input Dedicated global clock input pins that can also be used for the negative terminal inputs for differential global clock input or user input pins. Connect unused CLK or DIFFCLK pins to GND.
PLL[1..4]_CLKOUTp (Note 8) I/O, Output Optional positive terminal for external clock outputs from PLL [1..4]. Each pin can be assigned to single-ended or differential I/O standards if it is being fed by a PLL output. When not using this pin as a clock output, this pin may be used as a user I/O. When not using these pins, connect them as defined in Intel® Quartus® Prime software.
PLL[1..4]_CLKOUTn (Note 8) I/O, Output Optional negative terminal for external clock outputs from PLL [1..4]. Each pin can be assigned to single-ended or differential I/O standards if it is being fed by a PLL output. When not using this pin as a clock output, this pin may be used as a user I/O. When not using these pins, connect them as defined in Intel® Quartus® Prime software.
DPCLK[0.11] DPCLK Dual-purpose DPCLK pins can connect to the global clock network for high-fanout control signals such as clocks, asynchronous clears, presets, and clock enables. When these I/O pins are not used, they can be tied to GND.
CDPCLK[0..7] CDPCLK Dual-purpose CDPCLK pins can connect to the global clock network for high-fanout control signals such as clocks, asynchronous clears, presets, and clock enables. Only one of the two CDPCLK in each corner can feed the clock control block at a time. The other pin can be used as general-purpose I/O pin. The CDPCLK signals incure more delay to the clock control block because they are multiplexed before driving into the clock control block. When these I/O pins are not used, they can be tied to GND.

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