Intel® Cyclone® 10 LP Device Family Pin Connection Guidelines

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ID 683137
Date 11/09/2020
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Intel® Cyclone® 10 LP Device Family Pin Connection Guidelines
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Intel® Cyclone® 10 LP Pin Connection Guidelines Power Supply Sharing Guidelines Document Revision History for the Intel® Cyclone® 10 LP Device Family Pin Connection Guidelines
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Clock and PLL Pins Configuration/JTAG Pins Differential I/O Pins Reference Pins Supply Pins Notes to Intel® Cyclone® 10 LP Pin Connection Guidelines
Intel® Cyclone® 10 LP Device Family Pin Connection Guidelines

Differential I/O Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 3.  Differential I/O Pins
Pin Name Pin Functions Pin Description Connection Guidelines
DIFFIO_[L,R,T,B][0..61][p,n] (Note 11) I/O, TX/RX channel Dual-purpose differential transmitter/receiver channels. These channels can be used for transmitting/receiving LVDS compatible signals. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. Connect unused pins as defined in the Intel® Quartus® Prime software.
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