Intel® Cyclone® 10 LP Device Family Pin Connection Guidelines

ID 683137
Date 11/09/2020
Public

Configuration/JTAG Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 2.  Configuration/JTAG Pins
Pin Name Pin Functions Pin Description Connection Guidelines
MSEL[0..3] Input Configuration input pins that set the configuration scheme. Some of the smaller Intel® Cyclone® 10 LP devices or package options do not support AS configuration with fast delay (3.0V/2.5V) and do not have the MSEL[3] pin. These pins are internally connected through a 9-KΩ resistor to GND. Do not leave these pins floating. When these pins are unused, connect them to GND. Depending on the configuration scheme used, these pins should be tied to VCCA or GND. Refer to the "Configuration and Remote System Upgrades in Intel® Cyclone® 10 LP Devices" chapter in the Intel® Cyclone® 10 LP Handbook. If only JTAG configuration is used, connect these pins to GND.
nCE Input Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled. In a multi-device configuration, nCE of the first device is tied low while its nCEO pin drives the nCE of the next device in the chain. In single device configuration and JTAG programming, nCE should be connected to GND.
nCONFIG Input Dedicated configuration control input. Pulling this pin low during user-mode will cause the FPGA to lose its configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a logic high level will initiate reconfiguration. If you are using PS configuration scheme with a download cable, connect this pin through a 10-KΩ resistor to VCCA. For other configuration schemes, if this pin is not used, this pin must be connected directly or through a 10-KΩ resistor to VCCIO.
CONF_DONE Bidirectional (open-drain) This is a dedicated configuration status pin. As a status output, the CONF_DONE pin drives low before and during configuration. Once all configuration data is received without error and the initialization cycle starts, CONF_DONE is released. As a status input, CONF_DONE goes high after all data is received. Then the device initializes and enters user mode. This pin is not available as a user I/O pin. CONF_DONE should be pulled high by an external 10-KΩ pull-up resistor.
nCEO I/O, Output (open-drain) Output that drives low when device configuration is complete. This pin can be used as a regular I/O if not used for device configuration. When not using this pin, you can leave it unconnected. During multi-device configuration, this pin feeds the nCE pin of a subsequent device. In this case, tie the 10-KΩ pull-up resistor to an acceptable voltage for all devices in the chain which satisfies the input voltage of the receiving device. During single device configuration, this pin can be used as a regular I/O.
nSTATUS Bidirectional (open-drain) This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after power-up and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during configuration. As a status input, the device enters an error state when nSTATUS is driven low by an external source during configuration or initialization. This pin is not available as a user I/O pin. nSTATUS should be pulled high by an external 10-KΩ pull-up resistor.
TCK Input Dedicated JTAG test clock input pin. Connect this pin through a 1-KΩ pull-down resistor to GND. To disable the JTAG circuitry, connect TCK to GND.
TMS Input Dedicated JTAG test mode select input pin. When interfacing with 2.5 V, 3.0 V, or 3.3 V configuration voltage standard, connect this pin through a 10-kΩ resistor to VCCA. For configuration voltage of 1.5 V and 1.8 V, connect this pin through a 10-kΩ resistor to VCCIO supply instead.
TDI Input Dedicated JTAG test data input pin. When interfacing with 2.5 V, 3.0 V, or 3.3 V configuration voltage standard, connect this pin through a 10-kΩ resistor to VCCA. For configuration voltage of 1.5 V and 1.8 V, connect this pin through a 10-kΩ resistor to VCCIO supply instead.
TDO Output Dedicated JTAG test data output pin. If the TDO pin is not used, leave this pin unconnected.
nCSO I/O, Output (AS)

This pin functions as nCSO in AS mode.

nCSO: Output control signal from the FPGA to the serial configuration device in AS mode that enables the configuration device.

When not programming the device in AS mode, nCSO is not used. If the pin is not used as an I/O, you should leave the pin unconnected.
DATA1, ASDO Input (FPP), Output (AS)

This pin functions as DATA1 in PS and FPP modes, and as ASDO in AS mode.

DATA1: Data input in non-AS mode. Byte-wide configuration data is presented to the target device on DATA[0..7]. In PS configuration scheme, DATA1 functions as user I/O pin during configuration, which means it is tri-stated. After FPP configuration, DATA1 is available as a user I/O pin and the state of this pin depends on the Dual- Purpose Pin settings.

ASDO: Control signal from the FPGA to the serial configuration device in AS mode that is used to read out configuration data.

When not programming the device in AS mode, this pin is available as a user I/O pin. If the pin is not used as an I/O, then you should leave the pin unconnected.
DATA[2..7] Input (FPP) Data inputs. Byte-wide or word-wide configuration data is presented to the target device on DATA[0..7]. In AS or PS configuration scheme, they function as user I/O pins during configuration, which means they are tri-stated. After FPP configuration, DATA [2..7] are available as user I/O pins and the state of these pins depends on the Dual-Purpose Pin settings. When not programming the device in FPP mode, these pins are available as user I/O pins. If the pin is not used as an I/O you should leave the pin unconnected.
DCLK Input (PS, FPP), Output (AS) Dedicated configuration clock pin. In PS and FPP configuration, DCLK is used to clock configuration data from an external source into the FPGA. In AS mode, DCLK is an output from the FPGA that provides timing for the configuration interface. Do not leave this pin floating. Drive this pin either high or low. You can configure DCLK as a user I/O only after active serial configuration.
CRC_ERROR (Notes 13 and 15) I/O, Output Active high signal that indicates that the error detection circuit has detected errors in the configuration SRAM bits. This pin is optional and is used when the CRC error detection circuit is enabled. This pin can be used as regular I/O if not used for CRC error detection. The CRC_ERROR pin is a dedicated output by default. Optionally, you can enable the CRC_ERROR pin as an open-drain output in the Device & Pin option dialog box in the Intel® Quartus® Prime software. When using this pin, connect it through an external 10-KΩ pull-up resistor to an acceptable voltage for all devices in the chain that satisfies the input voltage of the receiving device. When not using this pin, it can be left floating.
DEV_CLRn I/O (when option off), Input (when option on) Optional pin that allows designers to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as programmed. This pin is enabled by turning on the Enable device-wide reset (DEV_CLRn) option in the Intel® Quartus® Prime software. When the dedicated input DEV_CLRn is not used and this pin is not used as an I/O, tie this pin to GND.
DEV_OE I/O (when option off), Input (when option on) Optional pin that allows designers to override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as defined in the design. This pin is enabled by turning on the Enable device-wide output enable (DEV_OE) option in the Intel® Quartus® Prime software. When the dedicated input DEV_OE is not used and this pin is not used as an I/O, then you should tie this pin to GND.
DATA0 Input (PS, FPP, AS) Dedicated configuration data input pin. In serial configuration modes, bit-wide configuration data is received through this pin. After AS configuration, DATA0 is a dedicated input pin with optional user control. After PS or FPP configuration, DATA0 is available as a user I/O pin and the state of this pin depends on the Dual-Purpose Pin settings. If you are using a serial configuration device in AS configuration mode, you must connect a 25-Ω series resistor at the near end of the serial configuration device for the DATA0. When the dedicated input for DATA0 is not used and this pin is not used as an I/O, then you must leave this pin unconnected.
INIT_DONE I/O, Output (open-drain) This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a transition from low to high at the pin indicates when the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration. This pin is enabled by turning on the Enable INIT_DONE output option in the Intel® Quartus® Prime software. When using this pin, connect it through an external 10-KΩ pull-up resistor to an acceptable voltage for all devices in the chain that satisfies the input voltage of the receiving device. When not using this pin, it can be left floating or tied to GND.
CLKUSR I/O, Input Optional user-supplied clock input. Synchronizes the initialization of one or more devices. If this pin is not enabled for use as a user-supplied configuration clock, it can be used as a user I/O pin. This pin is enabled by turning on the Enable user-supplied start-up clock (CLKUSR) option in the Intel® Quartus® Prime software. If the CLKUSR pin is not used as a configuration clock input and the pin is not used as an I/O, then you should connect this pin to GND.

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