Notes to Intel® Cyclone® 10 LP Pin Connection Guidelines
- FPP configuration is supported in most devices, except for the E144 package.
- Capacitance values for the power supply decoupling capacitors should be selected after consideration of the amount of power needed to supply over the frequency of operation of the particular circuit being decoupled. A target impedance for the power plane should be calculated based on current draw and voltage drop requirements of the device/supply. The power plane should then be decoupled using the appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Proper board design techniques such as interplane capacitance with low inductance should be considered for higher frequency decoupling. To assist in decoupling analysis, Power Distribution Network (PDN) Design Tool serves as an excellent decoupling analysis tool.
- For AC-coupled links, the AC-coupling capacitor can be placed anywhere along the channel. PCI Express protocol requires the AC-coupling capacitor to be placed on the transmitter side of the interface that permits adapters to be plugged and unplugged.
- Use the Intel® Cyclone® 10 LP Early Power Estimator to determine the current requirements for VCCINT and other power supplies.
- These supplies may share power planes across multiple Intel® Cyclone® 10 LP devices.
- Use separate power regulators for VCCA and VCCD_PLL. PLL power supply may originate from another plane on the board but must be isolated using a ferrite bead or other equivalent methods. If using a ferrite bead, choose an 0402 package with low DC resistance, higher current rating than the maximum steady state current for the supply it is connected to (VCCA or VCCD_PLL) and high impedance at 100 MHz.
- The number of dedicated global clocks for each device density is different. Please refer to the "Clock Networks and PLLs in Intel® Cyclone® 10 LP Devices" chapter in the Intel® Cyclone® 10 LP Device Handbook.
- The number of PLLs consisting of GPLLs and MPLLs for each device density is different. 10CL006 and 10CL010 support 2 PLLs. 10CL016 and other larger Intel® Cyclone® 10 LP densities support 4 PLLs.
- VCCA may use a switching regulator with a voltage ripple of ± 3% maximum. VCCD_PLL may use a switching power supply with a voltage ripple of ± 3 % maximum.
- You must follow specific requirements when interfacing Intel® Cyclone® 10 LP device with 2.5 V/3.0 V/3.3 V configuration voltage standards. All I/O inputs must maintain a maximum AC voltage of 4.1 V. Refer to Configuration and JTAG Pin I/O Requirements of the "Configuration and Remote System Upgrades in Intel® Cyclone® 10 LP Devices" chapter.
- The differential TX/RX channels for each device density and package is different. Please refer to the "I/O Features in Intel® Cyclone® 10 LP Devices" chapter in the Intel® Cyclone® 10 LP Device Handbook.
- Intel® highly recommends using an independent PCB via for each independent power or ground ball on the package. Sharing power or ground pin vias on the PCB could lead to noise coupling into the device and result in reduced jitter performance.
- CRC error detection is only supported in Intel® Cyclone® 10 LP devices with VCCINT 1.2 V, and not in Intel® Cyclone® 10 LP devices with VCCINT 1.0 V.
- The Intel® Quartus® Prime*.pin file created after compiling the design project in the Intel® Quartus® Prime software lists unused clock input pins as GND+ (unused input clocks and PLLs). Verify that any pins listed as such in the Intel® Quartus® Prime*.pin file are connected to the board as indicated in these recommendations.
- There are two variants of Intel® Cyclone® 10 LP devices; one powered with core voltage VCCINT 1.0 V, and another powered with core voltage VCCINT 1.2 V. Each variant has different ordering codes.
- The number of optional high speed differential reference clock input for each device density is different.