Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Document Table of Contents
Give Feedback Passive Serial Single-Device Configuration Using an External Host

To configure Intel® Cyclone® 10 LP device, connect the device to an external host.

Figure 88. Single Device PS Configuration Using an External Host

You can use the external host to control the transfer of configuration data from an external storage such as flash memory to the FPGA. The design that controls the configuration process resides in the external host.

You can store the configuration data in .rbf, .hex, or .ttf.

  1. The configuration begins when the external host device generates a low-to-high transition on the nCONFIG pin.
  2. When nSTATUS is high, the external host device places the configuration data one bit at a time on DATA[0].
  3. If you are using configuration data in .rbf, .hex, or .ttf, send the LSB of each data byte first. For example, if the .rbf contains the byte sequence 02 1B EE 01 FA, the serial data you must send to the device is:
    0100-0000 1101-1000 0111-0111 1000-0000 0101-1111
  4. The Intel® Cyclone® 10 LP device receives configuration data on DATA[0] and clock on DCLK.
  5. The configuration data latches onto the device on the rising edge of DCLK.
  6. The data continuously clocks into the target device until CONF_DONE goes high and the device enters initialization state.
    Note: Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device.
  7. When initialization completes, INIT_DONE releases and goes high. The external host device must be able to detect this low-to-high transition signal, which indicates the device has entered user mode.
    Note: In user mode, the user I/O pins no longer have weak pull-up resistors and function as assigned in your design.
To ensure DCLK and DATA[0] are not left floating at the end of configuration, the external processor must drive them high or low, depending on your board. The DATA[0] pin is available as a user I/O pin after configuration. In the PS scheme, the DATA[0] pin is tri-stated by default in user mode and must be driven by the external host device.
  • The configuration clock (DCLK) speed must be below the specified system frequency to ensure correct configuration.
  • You can pause configuration by halting DCLK for an indefinite amount of time because there is no maximum DCLK period.
The external host device also monitors CONF_DONE and INIT_DONE to ensure successful configuration.
  • The CONF_DONE pin must be monitored by the external device to detect errors and to determine when programming is complete.
  • If all configuration data is sent, but CONF_DONE or INIT_DONE has not gone high, the external device must reconfigure the target device.