Visible to Intel only — GUID: tbs1485173174619
Ixiasoft
Visible to Intel only — GUID: tbs1485173174619
Ixiasoft
6.1.4.3. JTAG Single-Device Configuration
To configure a single device in a JTAG chain, the programing software sets the other devices to bypass mode. A device in a bypass mode transfers the programming data from the TDI pin to the TDO pin through a single bypass register. The configuration data is available on the TDO pin one clock cycle later.
The Intel® Quartus® Prime software uses the CONF_DONE pin to verify the completion of the configuration process through the JTAG port:
- CONF_DONE pin is low—indicates that configuration has failed.
- CONF_DONE pin is high—indicates that configuration was successful.
After the configuration data is transmitted serially using the JTAG TDI port, the TCK port clocks additional cycles to perform device initialization.
- For device using VCCIO of 2.5, 3.0, and 3.3 V, all I/O inputs must maintain a maximum AC voltage of 4.1 V because JTAG pins do not have the internal PCI clamping diodes to prevent voltage overshoot. You must power up the VCC of the download cable with a 2.5-V supply from VCCA
- For device using VCCIO of 1.2 V, 1.5 V, and 1.8 V, you can power up the VCC of the download cable with the supply from VCCIO.
To configure Intel® Cyclone® 10 LP device using a microprocessor, connect the device as shown in the following figure.