Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Public
Document Table of Contents

6.1.4.3. JTAG Single-Device Configuration

To configure a single device in a JTAG chain, the programing software sets the other devices to bypass mode. A device in a bypass mode transfers the programming data from the TDI pin to the TDO pin through a single bypass register. The configuration data is available on the TDO pin one clock cycle later.

The Intel® Quartus® Prime software uses the CONF_DONE pin to verify the completion of the configuration process through the JTAG port:

  • CONF_DONE pin is low—indicates that configuration has failed.
  • CONF_DONE pin is high—indicates that configuration was successful.

After the configuration data is transmitted serially using the JTAG TDI port, the TCK port clocks additional cycles to perform device initialization.

To configure Intel® Cyclone® 10 LP device using an Intel FPGA download cable, connect the device as shown in the following figure.
  • For device using VCCIO of 2.5, 3.0, and 3.3 V, all I/O inputs must maintain a maximum AC voltage of 4.1 V because JTAG pins do not have the internal PCI clamping diodes to prevent voltage overshoot. You must power up the VCC of the download cable with a 2.5-V supply from VCCA
  • For device using VCCIO of 1.2 V, 1.5 V, and 1.8 V, you can power up the VCC of the download cable with the supply from VCCIO.
Figure 96. JTAG Configuration of a Single Device Using a Download Cable

To configure Intel® Cyclone® 10 LP device using a microprocessor, connect the device as shown in the following figure.

Figure 97. JTAG Configuration of a Single Device Using a Microprocessor
Note: Connect the nCONFIG and MSEL pins to support a non-JTAG configuration scheme. If you only use a JTAG configuration, connect the nCONFIG pin to logic-high and the MSEL pins to GND. Pull DCLK and DATA[0] to either high or low, whichever is convenient on your board.