Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

6.6. Configuration and Remote System Upgrades in Intel® Cyclone® 10 LP Devices Revision History

Document Version Changes
2021.08.18 Added a note to Passive Serial Configuration.
2020.12.03 Updated the following figures:
  • Figure: Single Device PS Configuration Using an External Host
  • Figure: Multi-Device PS Configuration Using an External Host
  • Figure: Multiple Device PS Configuration When Both Devices Receive the Same Configuration Data
2020.04.29 Corrected TMS pull up connection in the JTAG Configuration of Multiple Devices Using a Download Cable diagram.
2019.12.23 Updated Figure: AS Configuration Timing Waveform.
2019.01.24

Added a link to the Intel® Supported Configuration Devices section of the Device Configuration - Support Center page on the Intel® website.

2018.10.22
  • Updated the notes in the Fast Passive Parallel Configuration topic.
  • Updated the diagram that shows the combination of JTAG and AS configuration schemes to correct the resistor value connected to the TCK pin from 10 kΩ to 1 kΩ.
2018.05.07
  • Added the FPP Configuration Timing Waveform, AS Configuration Timing Waveform, and PS Configuration Timing Waveform.
  • Added the DEV_OE pin to the Configuration Pins Summary for Intel® Cyclone® 10 LP Devices table.
  • Updated the CLKUSR and nCEO pin information in the Configuration Pins Summary for Intel® Cyclone® 10 LP Devices table.
  • Removed the FLASH_nCE pin from the Configuration Pins Summary for Intel® Cyclone® 10 LP Devices table.
  • Removed the 2.5-V configuration voltage standard support for the AS configuration scheme in the MSEL Pin Settings for Each Configuration Scheme of Intel® Cyclone® 10 LP Devices with MSEL[3:0] Pins table, MSEL Pin Settings for AS Configuration Scheme with MSEL[2:0] Pins table, and AS Configuration Guidelines section.
Date Version Changes
December 2017 2017.12.22
  • Edited the MSEL Pin Settings for Each Configuration Scheme of Intel® Cyclone® 10 LP Devices table. The voltage listed should refer to the configuration voltage standard.
  • Edited the typo in the Programming Serial Configuration Devices In-System Using the JTAG Interface figure. The resistor connected to the DATA pin should be 25 ohm.
May 2017 2017.05.08 Initial release.

Did you find the information on this page useful?

Characters remaining:

Feedback Message