Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 2/15/2023
Public
Document Table of Contents

5.4.1. Intel® Cyclone® 10 LP I/O Banks Architecture

The device I/O pins are grouped into eight groups and each group is associated with an I/O bank. Every I/O bank in the device has a separate power bus.

The only exception is HSTL-12 Class II, which is only supported in column I/O banks.

There are two types of I/O banks in Intel® Cyclone® 10 LP devices:

  • Row I/O banks—I/O banks 1, 2, 5, and 6, located on the left and right side of the device
  • Column I/O banks—I/O banks 3, 4, 7, and 8, located on the top and bottom side of the device

Only the column I/O banks support the 1.2 V HSTL Class II I/O standard. Both row and column I/O banks support all the other single-ended and differential I/O standards that the Intel® Cyclone® 10 LP device supports.