Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

4.1.5. GCLK Network Power Down

You can disable an Intel® Cyclone® 10 LP device’s GCLK (power down) using both static and dynamic approaches. In the static approach, configuration bits are set in the configuration file generated by the Intel® Quartus® Prime software, which automatically disables unused GCLKs. The dynamic clock enable or disable feature allows internal logic to control clock enable or disable the GCLKs in Intel® Cyclone® 10 LP devices.

When a clock network is disabled, all the logic fed by the clock network is in an off-state, thereby reducing the overall power consumption of the device. This function is independent of the PLL and is applied directly on the clock network.

You can set the input clock sources and the clkena signals for the GCLK multiplexers through the Intel® Quartus® Prime software using the ALTCLKCTRL IP core.

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