Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

4.2.11. Programmable Phase Shift

Phase shift is used to implement a robust solution for clock delays in Intel® Cyclone® 10 LP devices. Phase shift is implemented with a combination of the VCO phase output and the counter starting time. The VCO phase output and counter starting time are the most accurate methods of inserting delays, because they are based only on counter settings that are independent of process, voltage, and temperature.

You can phase shift the output clocks from the Intel® Cyclone® 10 LP PLLs in one of two ways:

  • Fine resolution using VCO phase taps
  • Coarse resolution using counter starting time

Fine resolution phase shifts are implemented by allowing any of the output counters (C[4..0]) or the M counter to use any of the eight phases of the VCO as the reference clock. This allows you to adjust the delay time with a fine resolution.

The following equation shows the minimum delay time that you can insert using this method.

Figure 53. Fine Resolution Phase Shift EquationfREF in this equation is the input reference clock frequency

For example, if fREF is 100 MHz, N = 1, and M = 8, then fVCO = 800 MHz, and Φfine = 156.25 ps. The PLL operating frequency defines this phase shift, a value that depends on reference clock frequency and counter settings.

Coarse resolution phase shifts are implemented by delaying the start of the counters for a predetermined number of counter clocks.

Figure 54. Coarse Resolution Phase Shift Equation C in this equation is the count value set for the counter delay time—the initial setting in the PLL usage section of the compilation report in the Intel® Quartus® Prime software. If the initial value is 1, C – 1 = 0° phase shift.
Figure 55. Example of Delay Insertion Using VCO Phase Output and Counter Delay TimeThe observations in this example are as follows:
  • CLK0 is based on 0° phase from the VCO and has the C value for the counter set to one.
  • CLK1 signal is divided by four, two VCO clocks for high time and two VCO clocks for low time. CLK1 is based on the 135° phase tap from the VCO and has the C value for the counter set to one.
  • CLK2 signal is also divided by four. In this case, the two clocks are offset by 3 Φfine. CLK2 is based on the 0° phase from the VCO but has the C value for the counter set to three. This creates a delay of two Φcoarse (two complete VCO periods).

You can use the coarse and fine phase shifts to implement clock delays in Intel® Cyclone® 10 LP devices.

Intel® Cyclone® 10 LP devices support dynamic phase shifting of VCO phase taps only. The phase shift is configurable for any number of times. Each phase shift takes about one scanclk cycle, allowing you to implement large phase shifts quickly.

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