Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

5.8.2.5. Differential SSTL I/O Standard in Intel® Cyclone® 10 LP Devices

The Differential SSTL I/O standard is a memory-bus standard used for applications such as high-speed DDR SDRAM interfaces.
Note: Intel does not validate or support any IP that is intended for memory application, such as DDR, in Intel® Cyclone® 10 LP devices.

Intel® Cyclone® 10 LP devices support Differential SSTL-2 and Differential SSTL-18 I/O standards. The Differential SSTL output standard is only supported at the PLL#_CLKOUT pins using two single-ended SSTL output buffers (PLL#_CLKOUTp and PLL#_CLKOUTn), with the second output programmed to have opposite polarity.

The Differential SSTL input standard is supported on the GCLK pins only, treating differential inputs as two single-ended SSTL and only decoding one of them.

The Differential SSTL I/O standard requires two differential inputs with an external reference voltage (VREF) and an external termination voltage (VTT) of 0.5 × VCCIO to which termination resistors are connected.

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