Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

4.3. Clock Networks and PLLs in Intel® Cyclone® 10 LP Devices Revision History

Document Version Changes
2018.10.22
  • Updated the Example of Automatic Switchover After Loss of Clock Detection diagram.
2018.05.07
  • Removed the note to the CLK[n] pin in the Clock Control Block diagram. The CLK0 pin is available in the Intel® Cyclone® 10 LP devices. Note removed: CLK[n] is not available on the left side of the Intel® Cyclone® 10 LP devices.
  • Updated the clock pin to CLK[3..0] on the left side of the Intel® Cyclone® 10 LP devices in the Clock Networks and Clock Control Block Locations in Intel® Cyclone® 10 LP Devices diagram.
Date Version Changes
December 2017 2017.12.22
  • Updated the dedicated clock pins in the Clock Networks section.
  • Added GCLK resources for CLK0/DIFFCLK_0p and CLK1/DIFFCLK_0n in the Intel® Cyclone® 10 LP Clock Sources Connectivity to the GCLK Networks table.
May 2017 2017.05.08 Initial release.

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