Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

2.2.4. Byte Enable

If you implement the M9K memory as RAM blocks, the embedded memory supports the byte enable features.

The byte enable features mask the input data to enable the writing of only specific bytes. The unwritten bytes retain the previous values. The write enable signal, wren, together with the byte enable signal, byteena, control the write operations on the RAM blocks. By default, the byteena signal is enabled (high) and only the wren signal controls the writing.

The M9K blocks support byte enables when the write port has a data width of ×16, ×18, ×32, or ×36 bits. In True Dual-Port memory configuration, byte enables are available only if both PortA and PortB data widths of each M9K memory blocks are multiples of 8 or 9 bits.

Byte enables operate in a one-hot fashion. The LSB of the byteena signal corresponds to the LSB of the data bus. For example, if byteena = 01 and you are using a RAM block in ×18 mode, data[8:0] is enabled and data[17:9] is disabled. Similarly, if byteena = 11, both data[8:0] and data[17:9] are enabled.

Byte enables are active high. The byte enable registers do not have a clear port.

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