Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

6.2.3. Configuration and JTAG Pin I/O Requirements

Intel® Cyclone® 10 LP devices are manufactured using the TSMC 60-nm low-k dielectric process. Although the Intel® Cyclone® 10 LP devices use TSMC 2.5 V transistor technology in the I/O buffers, the devices are compatible and able to interface with 2.5 V, 3.0 V, and 3.3 V configuration voltage standards by following specific requirements.

All I/O inputs must maintain a maximum AC voltage of 4.1 V.
  • When using a serial configuration device in an AS configuration scheme, you must connect a 25 Ω series resistor for the DATA[0] pin.
  • When cascading the Intel® Cyclone® 10 LP device family in a multi-device configuration for AS, FPP, and PS configuration schemes, you must connect the repeater buffers between the master and slave devices for the DATA and DCLK pins.
  • When using the JTAG configuration scheme in a multi-device configuration, connect 25 Ω resistors on both ends of the TDO-TDI path if the TDO output driver is not an Intel® Cyclone® 10 LP device.
The output resistance of the repeater buffers and the TDO path for all cases must fit the maximum overshoot equation below:

Note: is the transmission line impedance and is the equivalent resistance of the output buffer.

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