Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

4.2.2. PLL Architecture

Figure 42.  Intel® Cyclone® 10 LP PLL Block DiagramEach clock source can come from any of the four clock pins located on the same side of the device as the PLL.

The VCO post-scale counter, K, is used to divide the supported VCO range by two. The VCO frequency reported by the Intel® Quartus® Prime software in the PLL summary section of the compilation report takes into consideration the VCO post-scale counter value. Therefore, if the VCO post-scale counter has a value of 2, the frequency reported is lower than the fVCO specification specified in the Intel® Cyclone® 10 LP Device Datasheet.

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