Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Document Table of Contents

7.4.2. Accessing Error Detection Block Through User Logic

You can also enable error detection through the user logic in the Intel® Cyclone® 10 LP devices.

The error detection circuitry stores the computed 32-bit CRC signature in a 32-bit register, which is read out by user logic from the core.

The cyclone10lp_crcblock primitive is a WYSIWYG component used to establish the interface from the user logic to the error detection circuit. The cyclone10lp_crcblock primitive atom contains the input and output ports that must be included in the atom.

To access the logic array, insert the cyclone10lp_crcblock WYSIWYG atom into your design.

Figure 110. The Error Detection Block Interfacing with the WYSIWYG Atom
Note: Any soft error failure affects the user logic. Therefore, do not rely on the regout signal in the 32-bit CRC signature to detect a soft error. The CRC_ERROR output signal provides a more accurate reading because is it not affected by a soft error.
Table 57.  CRC Block Input and Output Ports
Port Direction Description
<crcblock_name> Input

Unique identifier for the CRC block, and represents any identifier name that is legal for the given description language (e.g. Verilog HDL, VHDL, and AHDL).

This field is required.

.clk(<clock source>) Input

This signal designates the clock input of this cell. All operations of this cell relate to the rising edge of the clock. Whether it is the loading of the data into the cell or data out of the cell, it always occurs on the rising edge.

This port is required.

.shiftnld (<shiftnld source>) Input

This signal is an input into the error detection block.

  • If shiftnld=1, the data shifts from the internal shift register to the regout at each rising edge of clk.
  • If shiftnld=0, the shift register parallel loads either the pre-calculated CRC value or the update register contents, depending on the ldsrc port input. To do this, shiftnld must be driven low for at least two clock cycles.

This port is required.

.ldsrc(<ldsrc source>) Input

This signal is an input into the error detection block.

  • While shiftnld=1, this port is ignored.
  • While shiftnld=0:
    • If ldsrc=0, the pre-computed CRC register gets selected for loading into the 32-bit shift register at the rising edge of clk when shiftnld=0.
    • If ldsrc=1, the signature register (result of the CRC calculation) gets selected for loading into the shift register at the rising edge of clk when shiftnld=0.

This port is required.

.crcerror (<crcerror indicator output>) Output

This signal is the output of the cell that synchronizes to the internal oscillator of the device (80 MHz internal oscillator) and not to the clk port. It asserts high if the error block detects that a SRAM bit has flipped and the internal CRC computation shows a difference value compared to the pre-computed value.

You must connect this signal either to an output pin or a bidirectional pin.

  • If it is connected to an output pin, you can only monitor the CRC_ERROR pin (the core cannot access this output).
  • If the CRC_ERROR signal is used by the core logic to read error detection logic, you must connect this signal to a BIDIR pin. The signal is fed to the core indirectly by feeding a BIDIR pin that has its output enable port connected to VCC.
.regout (<registered output>) Output

This signal is the output of the error detection shift register synchronized to the clk port to be read by the core logic. It shifts one bit at each cycle, so you should clock the clk signal 31 cycles to read out the 32 bits of the shift register.

To enable the cyclone10lp_crcblock WYSIWYG atom, name the atom for each Intel® Cyclone® 10 LP device accordingly.

Defining Input and Output Ports in a WYSIWYG Atom

.clk(<clock source>),
.shiftnld(<shiftnld source>),
.ldsrc(<ldsrc source>),
.crcerror(<crcerror out destination>),
.regout(<output destination>),

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