Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

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ID 683777
Date 2/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Logic Elements and Logic Array Blocks in Intel® Cyclone® 10 LP Devices 2. Embedded Memory Blocks in Intel® Cyclone® 10 LP Devices 3. Embedded Multipliers in Intel® Cyclone® 10 LP Devices 4. Clock Networks and PLLs in Intel® Cyclone® 10 LP Devices 5. I/O and High Speed I/O in Intel® Cyclone® 10 LP Devices 6. Configuration and Remote System Upgrades 7. SEU Mitigation in Intel® Cyclone® 10 LP Devices 8. JTAG Boundary-Scan Testing for Intel® Cyclone® 10 LP Devices 9. Power Management in Intel® Cyclone® 10 LP Devices
1. Logic Elements and Logic Array Blocks in Intel® Cyclone® 10 LP Devices x
1.1. Logic Elements 1.2. Logic Array Block 1.3. Logic Elements and Logic Array Blocks in Intel® Cyclone® 10 LP Devices Revision History
1.1. Logic Elements x
1.1.1. LE Features 1.1.2. LE Operating Modes
1.1.2. LE Operating Modes x
1.1.2.1. Normal Mode 1.1.2.2. Arithmetic Mode
1.2. Logic Array Block x
1.2.1. LAB Interconnects 1.2.2. LAB Control Signals
2. Embedded Memory Blocks in Intel® Cyclone® 10 LP Devices x
2.1. Embedded Memory Capacity 2.2. Intel® Cyclone® 10 LP Embedded Memory General Features 2.3. Intel® Cyclone® 10 LP Embedded Memory Operation Modes 2.4. Intel® Cyclone® 10 LP Embedded Memory Clock Modes 2.5. Intel® Cyclone® 10 LP Embedded Memory Configurations 2.6. Intel® Cyclone® 10 LP Embedded Memory Design Consideration 2.7. Embedded Memory Blocks in Intel® Cyclone® 10 LP Devices Revision History
2.2. Intel® Cyclone® 10 LP Embedded Memory General Features x
2.2.1. Control Signals 2.2.2. Parity Bit 2.2.3. Read Enable 2.2.4. Byte Enable 2.2.5. Read-During-Write 2.2.6. Packed Mode Support 2.2.7. Address Clock Enable Support 2.2.8. Asynchronous Clear
2.2.4. Byte Enable x
2.2.4.1. Byte Enable Controls 2.2.4.2. Data Byte Output 2.2.4.3. RAM Blocks Operations
2.2.8. Asynchronous Clear x
2.2.8.1. Resetting Registers in M9K Blocks
2.3. Intel® Cyclone® 10 LP Embedded Memory Operation Modes x
2.3.1. Supported Memory Operation Modes
2.3.1. Supported Memory Operation Modes x
2.3.1.1. RAM: 1-Port IP Core References 2.3.1.2. RAM: 2-PORT IP Core References 2.3.1.3. ROM: 1-PORT IP Core References 2.3.1.4. ROM: 2-PORT IP Core References 2.3.1.5. Shift Register (RAM-based) IP Core References 2.3.1.6. FIFO IP Core References
2.4. Intel® Cyclone® 10 LP Embedded Memory Clock Modes x
2.4.1. Asynchronous Clear in Clock Modes 2.4.2. Output Read Data in Simultaneous Read and Write 2.4.3. Independent Clock Enables in Clock Modes
2.5. Intel® Cyclone® 10 LP Embedded Memory Configurations x
2.5.1. Port Width Configurations 2.5.2. Memory Configurations for Dual-Port Modes 2.5.3. Maximum Block Depth Configuration
2.6. Intel® Cyclone® 10 LP Embedded Memory Design Consideration x
2.6.1. Implement External Conflict Resolution 2.6.2. Customize Read-During-Write Behavior 2.6.3. Consider Power-Up State and Memory Initialization 2.6.4. Control Clocking to Reduce Power Consumption 2.6.5. Selecting Read-During-Write Output Choices
2.6.2. Customize Read-During-Write Behavior x
2.6.2.1. Same-Port Read-During-Write Mode 2.6.2.2. Mixed-Port Read-During-Write Mode
2.6.2.2. Mixed-Port Read-During-Write Mode x
2.6.2.2.1. Mixed-Port Read-During-Write Operation with Dual Clocks
3. Embedded Multipliers in Intel® Cyclone® 10 LP Devices x
3.1. Embedded Multiplier Block Overview 3.2. Multipliers Resources in Intel® Cyclone® 10 LP Devices 3.3. Embedded Multipliers Architecture 3.4. Embedded Multipliers Operational Modes 3.5. Embedded Multipliers in Intel® Cyclone® 10 LP Devices Revision History
3.3. Embedded Multipliers Architecture x
3.3.1. Input Register 3.3.2. Multiplier Stage 3.3.3. Output Register
3.4. Embedded Multipliers Operational Modes x
3.4.1. 18-Bit Multipliers 3.4.2. 9-Bit Multipliers
4. Clock Networks and PLLs in Intel® Cyclone® 10 LP Devices x
4.1. Clock Networks 4.2. PLLs in Intel® Cyclone® 10 LP Devices 4.3. Clock Networks and PLLs in Intel® Cyclone® 10 LP Devices Revision History
4.1. Clock Networks x
4.1.1. GCLK Network 4.1.2. GCLK Network Sources 4.1.3. Clock Control Block 4.1.4. GCLK Network Clock Source Generation 4.1.5. GCLK Network Power Down 4.1.6. Clock Enable Signals
4.2. PLLs in Intel® Cyclone® 10 LP Devices x
4.2.1. PLL Features 4.2.2. PLL Architecture 4.2.3. External Clock Outputs 4.2.4. Clock Feedback Modes 4.2.5. Clock Multiplication and Division 4.2.6. Post-Scale Counter Cascading 4.2.7. Programmable Duty Cycle 4.2.8. PLL Control Signals 4.2.9. Clock Switchover 4.2.10. Programmable Bandwidth 4.2.11. Programmable Phase Shift 4.2.12. PLL Cascading 4.2.13. PLL Reconfiguration 4.2.14. Spread-Spectrum Clocking
4.2.4. Clock Feedback Modes x
4.2.4.1. Source Synchronous Mode 4.2.4.2. No Compensation Mode 4.2.4.3. Normal Mode 4.2.4.4. Zero-Delay Buffer Mode
4.2.9. Clock Switchover x
4.2.9.1. Automatic Clock Switchover 4.2.9.2. Manual Override 4.2.9.3. Manual Clock Switchover 4.2.9.4. Guidelines
4.2.13. PLL Reconfiguration x
4.2.13.1. PLL Reconfiguration Hardware 4.2.13.2. PLL Reconfiguration Implementation 4.2.13.3. Dynamic Phase Shift 4.2.13.4. Dynamic Phase Shift Implementation
4.2.13.1. PLL Reconfiguration Hardware x
4.2.13.1.1. Post-Scale Counters (C0 to C4) 4.2.13.1.2. Scan Chain 4.2.13.1.3. Charge Pump and Loop Filter 4.2.13.1.4. Bypassing PLL Counter
5. I/O and High Speed I/O in Intel® Cyclone® 10 LP Devices x
5.1. Intel® Cyclone® 10 LP I/O Standards Support 5.2. I/O Resources in Intel® Cyclone® 10 LP Devices 5.3. Intel FPGA I/O IP Cores for Intel® Cyclone® 10 LP Devices 5.4. Intel® Cyclone® 10 LP I/O Elements 5.5. Intel® Cyclone® 10 LP Clock Pins Input Support 5.6. Programmable IOE Features in Intel® Cyclone® 10 LP Devices 5.7. I/O Standards Termination 5.8. Intel® Cyclone® 10 LP High-Speed Differential I/Os and SERDES 5.9. Using the I/Os and High Speed I/Os in Intel® Cyclone® 10 LP Devices 5.10. I/O and High Speed I/O in Intel® Cyclone® 10 LP Devices Revision History
5.1. Intel® Cyclone® 10 LP I/O Standards Support x
5.1.1. Intel® Cyclone® 10 LP I/O Standards Voltage and Pin Support
5.2. I/O Resources in Intel® Cyclone® 10 LP Devices x
5.2.1. Intel® Cyclone® 10 LP Devices I/O Resources Per Package 5.2.2. Intel® Cyclone® 10 LP I/O Vertical Migration 5.2.3. Intel® Cyclone® 10 LP VREF Pins Per I/O Bank 5.2.4. Intel® Cyclone® 10 LP LVDS Channels Support
5.4. Intel® Cyclone® 10 LP I/O Elements x
5.4.1. Intel® Cyclone® 10 LP I/O Banks Architecture 5.4.2. Intel® Cyclone® 10 LP I/O Banks Locations
5.6. Programmable IOE Features in Intel® Cyclone® 10 LP Devices x
5.6.1. Programmable Open Drain 5.6.2. Programmable Bus Hold 5.6.3. Programmable Pull-Up Resistor 5.6.4. Programmable Current Strength 5.6.5. Programmable Output Slew Rate Control 5.6.6. Programmable IOE Delay 5.6.7. PCI Clamp Diode 5.6.8. Programmable Pre-Emphasis
5.7. I/O Standards Termination x
5.7.1. Voltage-Referenced I/O Standards Termination 5.7.2. Differential I/O Standards Termination 5.7.3. Intel® Cyclone® 10 LP On-Chip I/O Termination
5.7.3. Intel® Cyclone® 10 LP On-Chip I/O Termination x
5.7.3.1. OCT Calibration 5.7.3.2. RS OCT in Intel® Cyclone® 10 LP Devices
5.8. Intel® Cyclone® 10 LP High-Speed Differential I/Os and SERDES x
5.8.1. High-Speed Differential I/O Interface 5.8.2. Differential I/O Standards Support 5.8.3. High-Speed I/O Timing Budget
5.8.2. Differential I/O Standards Support x
5.8.2.1. LVDS I/O Standard in Intel® Cyclone® 10 LP Devices 5.8.2.2. Bus LVDS I/O Standard in Intel® Cyclone® 10 LP Devices 5.8.2.3. RSDS, Mini-LVDS, and PPDS I/O Standard in Intel® Cyclone® 10 LP Devices 5.8.2.4. LVPECL I/O Standard in Intel® Cyclone® 10 LP Devices 5.8.2.5. Differential SSTL I/O Standard in Intel® Cyclone® 10 LP Devices 5.8.2.6. Differential HSTL I/O Standard in Intel® Cyclone® 10 LP Devices
5.8.3. High-Speed I/O Timing Budget x
5.8.3.1. Receiver Input Skew Margin 5.8.3.2. RSKM Equation
5.9. Using the I/Os and High Speed I/Os in Intel® Cyclone® 10 LP Devices x
5.9.1. Guideline: Validate Your Pin Placement 5.9.2. Guideline: Check for Illegal Pad Placements 5.9.3. Guideline: Voltage-Referenced I/O Standards Restriction 5.9.4. Guideline: Simultaneous Usage of Multiple I/O Standards 5.9.5. Guideline: LVTTL or LVCMOS Inputs in Intel® Cyclone® 10 LP Devices 5.9.6. Guideline: Differential Pad Placement 5.9.7. Guideline: Board Design for Signal Quality
6. Configuration and Remote System Upgrades x
6.1. Configuration Schemes 6.2. Configuration Requirement 6.3. Configuration Details 6.4. Configuration Data Compression 6.5. Remote System Upgrades 6.6. Configuration and Remote System Upgrades in Intel® Cyclone® 10 LP Devices Revision History
6.1. Configuration Schemes x
6.1.1. Active Serial (AS) Configuration 6.1.2. Passive Serial Configuration 6.1.3. Fast Passive Parallel Configuration 6.1.4. JTAG Configuration
6.1.1. Active Serial (AS) Configuration x
6.1.1.1. Active Serial Single-Device Configuration 6.1.1.2. Active Serial Multi-Device Configuration 6.1.1.3. Configuring Multiple Intel® Cyclone® 10 LP Devices with the Same Design
6.1.1.3. Configuring Multiple Intel® Cyclone® 10 LP Devices with the Same Design x
6.1.1.3.1. Multiple .sof Files 6.1.1.3.2. Single .sof File
6.1.2. Passive Serial Configuration x
6.1.2.1. Passive Serial Single-Device Configuration Using an External Host 6.1.2.2. Passive Serial Multi-Device Configuration Using an External Host 6.1.2.3. Passive Serial Single-Device Configuration Using a Download Cable 6.1.2.4. Passive Serial Multi-Device Configuration Using a Download Cable
6.1.2.2. Passive Serial Multi-Device Configuration Using an External Host x
6.1.2.2.1. Passive Serial Multi Devices Using Same Configuration Data
6.1.3. Fast Passive Parallel Configuration x
6.1.3.1. Fast Passive Parallel Single-Device Configuration 6.1.3.2. Fast Passive Parallel Multi-Device Configuration
6.1.3.2. Fast Passive Parallel Multi-Device Configuration x
6.1.3.2.1. Fast Passive Parallel Multi Devices Using Same Configuration Data
6.1.4. JTAG Configuration x
6.1.4.1. Configuring Intel® Cyclone® 10 LP Devices with the JRunner Software Driver 6.1.4.2. Configuring Intel® Cyclone® 10 LP Devices with Jam STAPL 6.1.4.3. JTAG Single-Device Configuration 6.1.4.4. JTAG Multi-Device Configuration 6.1.4.5. Combining JTAG and AS Configuration Schemes 6.1.4.6. Programming Serial Configuration Devices In-System with the JTAG Interface 6.1.4.7. JTAG Instructions
6.1.4.6. Programming Serial Configuration Devices In-System with the JTAG Interface x
6.1.4.6.1. Loading the SFL Design 6.1.4.6.2. Configuring the Device 6.1.4.6.3. Reconfiguring the Device
6.1.4.7. JTAG Instructions x
6.1.4.7.1. CONFIG_IO 6.1.4.7.2. ACTIVE_DISENGAGE 6.1.4.7.3. ACTIVE_ENGAGE 6.1.4.7.4. Overriding the Internal Oscillator
6.1.4.7.4. Overriding the Internal Oscillator x
6.1.4.7.4.1. EN_ACTIVE_CLK 6.1.4.7.4.2. DIS_ACTIVE_CLK
6.2. Configuration Requirement x
6.2.1. Power-On Reset (POR) Circuit 6.2.2. Configuration File Size 6.2.3. Configuration and JTAG Pin I/O Requirements
6.3. Configuration Details x
6.3.1. MSEL Pin Settings 6.3.2. Configuration Sequence 6.3.3. Configuration Timing Waveforms 6.3.4. Device Configuration Pins
6.3.2. Configuration Sequence x
6.3.2.1. Power Up 6.3.2.2. Reset 6.3.2.3. Configuration 6.3.2.4. Configuration Error Handling 6.3.2.5. Initialization 6.3.2.6. User Mode
6.3.3. Configuration Timing Waveforms x
6.3.3.1. FPP Configuration Timing 6.3.3.2. AS Configuration Timing 6.3.3.3. PS Configuration Timing
6.4. Configuration Data Compression x
6.4.1. Enabling Compression Before Design Compilation 6.4.2. Enabling Compression After Design Compilation 6.4.3. Using Compression in Multi-Device Configuration
6.5. Remote System Upgrades x
6.5.1. Enabling Remote Update 6.5.2. Configuration Sequence in the Remote Update Mode 6.5.3. Remote System Upgrade Circuitry 6.5.4. Remote System Upgrade Registers 6.5.5. Remote System Upgrade State Machine 6.5.6. User Watchdog Timer
6.5.1. Enabling Remote Update x
6.5.1.1. Configuration Images
6.5.4. Remote System Upgrade Registers x
6.5.4.1. Control Register 6.5.4.2. Status Register
7. SEU Mitigation in Intel® Cyclone® 10 LP Devices x
7.1. Configuration Error Detection 7.2. User Mode Error Detection 7.3. Error Detection Features 7.4. Using Error Detection Features in User Mode 7.5. SEU Mitigation for Intel® Cyclone® 10 LP Devices Revision History
7.3. Error Detection Features x
7.3.1. Error Detection Block
7.3.1. Error Detection Block x
7.3.1.1. CRC_ERROR Pin 7.3.1.2. CHANGE_EDREG JTAG Instruction 7.3.1.3. Error Detection Timing 7.3.1.4. Error Detection Frequency 7.3.1.5. CRC Calculation Time
7.3.1.2. CHANGE_EDREG JTAG Instruction x
7.3.1.2.1. Example JAM File 7.3.1.2.2. Procedure
7.4. Using Error Detection Features in User Mode x
7.4.1. Enabling Error Detection 7.4.2. Accessing Error Detection Block Through User Logic Defining Input and Output Ports in a WYSIWYG Atom
8. JTAG Boundary-Scan Testing for Intel® Cyclone® 10 LP Devices x
8.1. BST Operation Control 8.2. I/O Voltage Support in the JTAG Chain 8.3. Boundary-Scan Description Language Support 8.4. JTAG Boundary-Scan Testing for Intel® Cyclone® 10 LP Devices Revision History
9. Power Management in Intel® Cyclone® 10 LP Devices x
9.1. External Power Supply Requirements 9.2. Hot-Socketing Specifications 9.3. Hot-Socketing Feature Implementation 9.4. Power-On Reset Circuitry 9.5. Power Management in Intel® Cyclone® 10 LP Devices Revision History
9.2. Hot-Socketing Specifications x
9.2.1. Drive Intel® Cyclone® 10 LP Devices Before Power Up 9.2.2. I/O Pins Remain Tri-stated During Power Up
1. Logic Elements and Logic Array Blocks in Intel® Cyclone® 10 LP Devices
2. Embedded Memory Blocks in Intel® Cyclone® 10 LP Devices
3. Embedded Multipliers in Intel® Cyclone® 10 LP Devices
4. Clock Networks and PLLs in Intel® Cyclone® 10 LP Devices
5. I/O and High Speed I/O in Intel® Cyclone® 10 LP Devices
6. Configuration and Remote System Upgrades
7. SEU Mitigation in Intel® Cyclone® 10 LP Devices
8. JTAG Boundary-Scan Testing for Intel® Cyclone® 10 LP Devices
9. Power Management in Intel® Cyclone® 10 LP Devices

7.4.2. Accessing Error Detection Block Through User Logic

You can also enable error detection through the user logic in the Intel® Cyclone® 10 LP devices.

The error detection circuitry stores the computed 32-bit CRC signature in a 32-bit register, which is read out by user logic from the core.

The cyclone10lp_crcblock primitive is a WYSIWYG component used to establish the interface from the user logic to the error detection circuit. The cyclone10lp_crcblock primitive atom contains the input and output ports that must be included in the atom.

To access the logic array, insert the cyclone10lp_crcblock WYSIWYG atom into your design.

Figure 110. The Error Detection Block Interfacing with the WYSIWYG Atom
Note: Any soft error failure affects the user logic. Therefore, do not rely on the regout signal in the 32-bit CRC signature to detect a soft error. The CRC_ERROR output signal provides a more accurate reading because is it not affected by a soft error.
Table 57.  CRC Block Input and Output Ports
Port Direction Description
<crcblock_name> Input

Unique identifier for the CRC block, and represents any identifier name that is legal for the given description language (e.g. Verilog HDL, VHDL, and AHDL).

This field is required.
.clk(<clock source>) Input

This signal designates the clock input of this cell. All operations of this cell relate to the rising edge of the clock. Whether it is the loading of the data into the cell or data out of the cell, it always occurs on the rising edge.

This port is required.
.shiftnld (<shiftnld source>) Input

This signal is an input into the error detection block.

  • If shiftnld=1, the data shifts from the internal shift register to the regout at each rising edge of clk.
  • If shiftnld=0, the shift register parallel loads either the pre-calculated CRC value or the update register contents, depending on the ldsrc port input. To do this, shiftnld must be driven low for at least two clock cycles.

This port is required.
.ldsrc(<ldsrc source>) Input

This signal is an input into the error detection block.

  • While shiftnld=1, this port is ignored.
  • While shiftnld=0:
    • If ldsrc=0, the pre-computed CRC register gets selected for loading into the 32-bit shift register at the rising edge of clk when shiftnld=0.
    • If ldsrc=1, the signature register (result of the CRC calculation) gets selected for loading into the shift register at the rising edge of clk when shiftnld=0.

This port is required.
.crcerror (<crcerror indicator output>) Output

This signal is the output of the cell that synchronizes to the internal oscillator of the device (80 MHz internal oscillator) and not to the clk port. It asserts high if the error block detects that a SRAM bit has flipped and the internal CRC computation shows a difference value compared to the pre-computed value.

You must connect this signal either to an output pin or a bidirectional pin.

  • If it is connected to an output pin, you can only monitor the CRC_ERROR pin (the core cannot access this output).
  • If the CRC_ERROR signal is used by the core logic to read error detection logic, you must connect this signal to a BIDIR pin. The signal is fed to the core indirectly by feeding a BIDIR pin that has its output enable port connected to VCC.
.regout (<registered output>) Output

This signal is the output of the error detection shift register synchronized to the clk port to be read by the core logic. It shifts one bit at each cycle, so you should clock the clk signal 31 cycles to read out the 32 bits of the shift register.

To enable the cyclone10lp_crcblock WYSIWYG atom, name the atom for each Intel® Cyclone® 10 LP device accordingly.

Defining Input and Output Ports in a WYSIWYG Atom

cyclone10lp_crcblock<crcblock_name>
(
.clk(<clock source>),
.shiftnld(<shiftnld source>),
.ldsrc(<ldsrc source>),
.crcerror(<crcerror out destination>),
.regout(<output destination>),
);
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