Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

ID 683777
Date 9/26/2022
Public
Document Table of Contents

5.8. Intel® Cyclone® 10 LP High-Speed Differential I/Os and SERDES

The Intel® Cyclone® 10 LP devices use registers and logic in the core fabric to implement LVDS input and output interfaces.
  • For LVDS transmitters, Intel® Cyclone® 10 LP devices use the double data rate I/O (DDIO) registers that reside in the I/O elements (IOE). For LVDS receivers, the devices use the DDIO registers in the core fabric. This architecture improves performance with regards to the receiver input skew margin (RSKM) or transmitter channel-to-channel skew (TCCS).
  • For the LVDS serializer/deserializer (SERDES), Intel® Cyclone® 10 LP devices use logic elements (LE) registers.
  • The device uses shift registers, internal phase-locked loops (PLLs), and I/O cells to perform serial-to-parallel conversions on incoming data and parallel-to-serial conversion on outgoing data.
Note: In Intel® Cyclone® 10 LP devices, the interface configured using the ALTLVDS IP core always sends the MSB of your parallel data first.

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